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參數資料
| 型號： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數： | 34/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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ATtiny40 [DATASHEET]
8263B–AVR–01/2013
correct address. If the received address is not a match, the slave will not acknowledge the address and wait for a
new START condition.
The slave Address/Stop Interrupt Flag is set when a START condition succeeded by a valid address packet is
detected. A general call address will also set the interrupt flag.
A START condition immediately followed by a STOP condition, is an illegal operation and the Bus Error flag is set.
The R/W Direction flag reflects the direction bit received with the address. This can be read by software to deter-
mine the type of operation currently in progress.
Depending on the R/W direction bit and bus condition one of four distinct cases (1 to 4) arises following the
address packet. The different cases must be handled in software.
17.4.1.1
Case 1: Address packet accepted - Direction bit set
If the R/W Direction flag is set, this indicates a master read operation. The SCL line is forced low, stretching the
bus clock. If ACK is sent by the slave, the slave hardware will set the Data Interrupt Flag indicating data is needed
for transmit. If NACK is sent by the slave, the slave will wait for a new START condition and address match.
17.4.1.2
Case 2: Address packet accepted - Direction bit cleared
If the R/W Direction flag is cleared this indicates a master write operation. The SCL line is forced low, stretching the
bus clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, Repeated START or STOP
can be received after this. If NACK is indicated the slave will wait for a new START condition and address match.
17.4.1.3
Case 3: Collision
If the slave is not able to send a high level or NACK, the Collision flag is set and it will disable the data and
acknowledge output from the slave logic. The clock hold is released. A START or repeated START condition will
be accepted.
17.4.1.4
Case 4: STOP condition received.
Operation is the same as case 1 or 2 above with one exception. When the STOP condition is received, the Slave
Address/Stop flag will be set indicating that a STOP condition and not an address match occurred.
17.4.2
Receiving Data Packets
The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received the Data Interrupt
Flag is set, and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a STOP or
Repeated START condition.
17.4.3
Transmitting Data Packets
The slave will know when an address packet, with R/W direction bit set, has been successfully received. It can then
start sending data by writing to the Slave Data register. When a data packet transmission is completed, the Data
Interrupt Flag is set. If the master indicates NACK, the slave must stop transmitting data, and expect a STOP or
Repeated START condition.
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