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參數(shù)資料
| 型號： | MR83C154XXX-30/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 27/204頁 |
| 文件大?。?/td> | 5687K |
| 代理商： | MR83C154XXX-30/883 |
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122
ATtiny40 [DATASHEET]
8263B–AVR–01/2013
16.5.3
SPDR – SPI Data Register
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift
Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive
buffer to be read.
17. TWI – Two Wire Interface (Slave)
17.1
Features
Phillips I2C compatible
SMBus compatible (with reservations)
100 kHz and 400 kHz support at low system clock frequencies
Slew-Rate Limited Output Drivers
Input Filter provides noise suppression
7-bit, and General Call Address Recognition in Hardware
Address mask register for address masking or dual address match
10-bit addressing supported
Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
Operates in all sleep modes, including Power Down
Slave Arbitration allows support for SMBus Address Resolve Protocol (ARP)
17.2
Overview
The Two Wire Interface (TWI) is a bi-directional, bus communication interface, which uses only two wires. The TWI
is I
2C compatible and, with reservations, SMBus compatible (see “Compatibility with SMBus” on page 128).
A device connected to the bus must act as a master or slave.The master initiates a data transaction by addressing
a slave on the bus, and telling whether it wants to transmit or receive data. One bus can have several masters, and
an arbitration process handles priority if two or more masters try to transmit at the same time.
The TWI module in ATtiny40 implements slave functionality, only. Lost arbitration, errors, collisions and clock holds
on the bus are detected in hardware and indicated in separate status flags.
Both 7-bit and general address call recognition is implemented in hardware. 10-bit addressing is also supported. A
dedicated address mask register can act as a second address match register or as a mask register for the slave
address to match on a range of addresses. The slave logic continues to operate in all sleep modes, including
Power down. This enables the slave to wake up from sleep on TWI address match. It is possible to disable the
address matching and let this be handled in software instead. This allows the slave to detect and respond to sev-
eral addresses. Smart Mode can be enabled to auto trigger operations and reduce software complexity.
The TWI module includes bus state logic that collects information to detect START and STOP conditions, bus col-
lision and bus errors. The bus state logic continues to operate in all sleep modes including Power down.
17.3
General TWI Bus Concepts
The Two-Wire Interface (TWI) provides a simple two-wire bi-directional bus consisting of a serial clock line (SCL)
and a serial data line (SDA). The two lines are open collector lines (wired-AND), and pull-up resistors (Rp) are the
only external components needed to drive the bus. The pull-up resistors will provide a high level on the lines when
none of the connected devices are driving the bus. A constant current source can be used as an alternative to the
pull-up resistors.
Bit
7654
3210
MSB
LSB
SPDR
Read/Write
R/W
Initial Value
XXXXXXXX
Undefined
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