
32-8
MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
Part V. The Communications Processor Module
The USB controller updates the frame number when an SOF token is received. The entry,
shown in Figure 32-5, contains 11 bits representing the frame number and a valid bit, which
is set if the SOF token is received without error. An SOF interrupt is issued when this entry
is updated.
1
Offset from endpoint parameter block base.
2
These parameters need not be accessed in normal operation but may be helpful for debugging.
Table 32-4. Endpoint Parameter Block
Offset
1
Name
Width
Description
0x00
RBASE
16 bits RxBD/TxBD base addresses. DeTne the starting location in dual-port RAM for the USB
controllers TxBDs and RxBDs. This provides exibility in how BDs are partitioned.
Setting W in the last BD in each list determines how many BDs to allocate for the
controllers send and receive sides. These entries must be initialized before the
controller is enabled. Overlapping USB BD tables with another serial controllers BDs
causes erratic operation. RBASE and TBASE values should be divisible by 8.
0x02
TBASE
16 bits
0x04
RFCR
8 bits
Rx/Tx function code. Controls the value to appear on AT[1D3] when the associated
SDMA channel accesses memory and the byte-ordering convention. See Figure 32-6.
0x05
TFCR
8 bits
0x06
MRBLR
16 bits Maximum receive buffer length. DeTnes the maximum number of bytes the MPC850
writes to the USB receive buffer before moving to the next buffer. MRBLR must be
divisible by 4. The MPC850 can write fewer bytes to the buffer than the MRBLR value if
a condition such as an error or end-of-packet occurs, but it never exceeds MRBLR.
Therefore, user-supplied buffers should never be smaller than MRBLR.
Transmit buffers for the USB controller are not affected by the MRBLR value. Transmit
buffer lengths can vary individually, as needed. The number of bytes to be sent is
chosen by programming TxBD[Data Length].
0x08
RBPTR
16 bits RxBD pointer. Points to the next BD the receiver will transfer data to when it is in an idle
state or to the current BD while processing a frame. Software should initialize RBPTR
after reset. When the end of the BD table is reached, the CP initializes this pointer to the
value programmed in RBASE. Although the user does not need to write RBPTR in most
applications (except initialization), it can be changed when the receiver is disabled or
when no receive buffer is being used.
0X0A
TBPTR
16 bits TxBD pointer. Points to the next BD that the transmitter will transfer data from when it is
in an idle state or to the current BD during frame transmission. TBPTR should be
initialized by the software after reset. When the end of BD table is reached, the CP
initializes this pointer to the value programmed in the TBASEn entry. Although the user
never needs to write TBPTR, in most applications (except initialization), it can be
changed when the transmitter is disabled or when no transmit buffer is being used.
0X0C
TSTATE
2
32 bits Tx internal state. Reserved for CP use only. Should be cleared before enabling the USB
controller.
0x10
TPTR
2
32 bits Tx internal data pointer. Updated by the SDMA channels to show the next address in
the buffer to be accessed.
0x14
TCRC
2
16 bits Tx temp CRC. Reserved for CP use only.
0x16
TBCNT
2
16 bits Tx internal byte count. A down-count value that is initialized with the TxBD data length
and decremented with every byte read by the SDMA channels.