
MOTOROLA
Chapter 15. Memory Controller
15-71
Part IV. The Hardware Interface
15.9.2 Page Mode Extended Data-Out Interface Example
Figure 15-63 shows the conTguration for a 1-Mbyte, 32-bit wide memory system using two
256K x 16-bit page mode EDO DRAMs. Also shown is the physical connection between
UPMB and the EDO DRAMs. The CS2 signal controlled by BR
x
is connected to both RAS
signals. The BS_B[0D1] signals map to D[0D15] and BS_B[2D3] map to D[16D31]. For this
connection, GPL_B1 is connected to the memory device OE pins. The refresh rate
calculation is based on a 25-MHz baud rate generator clock and the DRAM that requires a
512-cycle refresh every 8 ms.
This system has no external masters, and thus the MPC850 is conTgured to perform address
multiplexing internally.
Figure 15-63. EDO DRAM Interface Connection
Follow these steps to conTgure a system for EDO DRAM:
1. Determine the system architecture, which includes the MPC850 and the memory
system as shown in the example in Figure 15-64.
2. Use the blank work sheet in Figure 15-70 for timing diagrams. The timing diagrams
in Figure 15-64 through Figure 15-69 can be used as a reference.
3. Translate the timing diagrams into RAM words for each memory access type. The
bottom half of the Tgures show the RAM array contents that handle each of the
possible cycles; each column represents a different word in the RAM array. A blank
cell indicates a dont care bit (typically programmed to logic 1 to conserve power).
RAS
CASL
CASH
WE
MT4C16270
256K x 16
GPL_B1
R/W
CS2
BS_B[0–3]
RAS
CASL
CASH
WE
MT4C16270
256K x 16
BS_B0
BS_B1
BS_B2
BS_B3
D[0–15]
D[0–15]
D[0–15]
D[16–31]
OE
A[0–8]
A[0–8]
OE
A[21–29]
D[0–31]
2-Bit
2-Bit
8-Bit
8-Bit
MPC850