
MOTOROLA
Contents
xvii
CONTENTS
Paragraph
Number
Title
Page
Number
15.6.4.10
15.6.4.11
15.6.4.11.1
15.6.4.11.2
15.7
15.7.1
15.7.2
15.8
15.8.1
15.8.2
15.8.3
15.8.4
15.8.4.1
15.8.4.2
15.8.4.3
15.8.5
15.8.5.1
15.8.5.2
15.9
15.9.1
15.9.2
The Last Word (LAST)............................................................................15-49
The Wait Mechanism (WAEN) ...............................................................15-49
Internal and External Synchronous Masters........................................15-49
External Asynchronous Masters..........................................................15-50
Handling Devices with Slow or Variable Access Times .................................15-51
Hierarchical Bus Interface Example ............................................................15-52
Slow Devices Example ................................................................................15-52
External Master Support...................................................................................15-52
Synchronous External Masters.....................................................................15-52
Asynchronous External Masters ..................................................................15-53
Special Case: Address Type Signals for External Masters..........................15-53
UPM Features Supporting External Masters................................................15-53
Address Incrementing for External Synchronous Bursting Masters........15-53
Handshake Mechanism for Asynchronous Bursting Masters..................15-53
Special Signal for External Address Multiplexer Control.......................15-54
External Master Examples ...........................................................................15-54
External Masters and the GPCM .............................................................15-54
External Masters and the UPM................................................................15-55
Memory System Interface Examples ...............................................................15-60
Page-Mode DRAM Interface Example........................................................15-60
Page Mode Extended Data-Out Interface Example.....................................15-71
Chapter 16
PCMCIA Interface
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.4
16.4.1
16.4.2
16.4.3
System Configuration.........................................................................................16-1
PCMCIA Module Signal Definitions.................................................................16-1
PCMCIA Cycle Control Signals....................................................................16-2
PCMCIA Input Port Signals...........................................................................16-4
PCMCIA Output Port Signals (OP[0D4]) ......................................................16-4
Other PCMCIA Signals..................................................................................16-5
Operation Description........................................................................................16-5
Memory-Only Cards ......................................................................................16-5
I/O Cards........................................................................................................16-6
Interrupts........................................................................................................16-6
Power Control ................................................................................................16-7
Reset and Three-State Control.......................................................................16-7
DMA ..............................................................................................................16-7
Programming Model ..........................................................................................16-8
PCMCIA Interface Input Pins Register (PIPR) .............................................16-8
PCMCIA Interface Status Changed Register (PSCR) ...................................16-9
PCMCIA Interface Enable Register (PER)..................................................16-10