MOTOROLA
Illustrations
xlv
ILLUSTRATIONS
Figure
Number
Title
Page
Number
32-2
32-3
32-4
32-5
32-6
32-7
32-8
32-9
32-10
32-11
32-12
32-13
32-14
32-15
32-16
33-1
33-2
33-3
33-4
33-5
33-6
33-7
33-8
33-9
33-10
33-11
33-12
33-13
33-14
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
34-9
34-10
34-11
34-12
34-13
34-14
USB Interface..............................................................................................................32-4
USB Controller Operation Flow.................................................................................32-5
Endpoint Pointer Registers (EPnPTR)........................................................................32-7
Frame Number (FRAME_N)......................................................................................32-9
Transmit/Receive Function Code Registers (TFCR/RFCR).......................................32-9
USB Mode Register (USMOD)..................................................................................32-9
USB Slave Address Register (USADR)...................................................................32-10
USB Endpoint Registers 0D3 (USEPn).....................................................................32-11
USB Command Register (USCOM).........................................................................32-12
USB Event Register (USBER)/Mask Register (USBMR)........................................32-12
USB Status Register (USBS)....................................................................................32-13
USB Memory Structure............................................................................................32-15
USB Receive Buffer Descriptor (RxBD)..................................................................32-16
USB Transmit Buffer Descriptor (TxBD) ................................................................32-18
USB Command Format of the CPCR.......................................................................32-19
I
2
C Controller Block Diagram...................................................................................33-1
I
2
C Master/Slave General Configuration....................................................................33-2
I
2
C Transfer Timing ...................................................................................................33-3
I
2
C Master Write Timing............................................................................................33-4
I
2
C Master Read Timing.............................................................................................33-5
I
2
C Mode Register (I2MOD)......................................................................................33-6
I
2
C Address Register (I2ADD)...................................................................................33-7
I
2
C Baud Rate Generator Register (I2BRG) ..............................................................33-7
I
2
C Event/Mask Registers (I2CER/I2CMR) ..............................................................33-8
I
2
C Command Register (I2COM)...............................................................................33-9
I
2
C Function Code Registers (RFCR/TFCR)...........................................................33-11
I
2
C Memory Structure..............................................................................................33-12
I
2
C Receive Buffer Descriptor (RxBD)....................................................................33-13
I
2
C Transmit Buffer Descriptor (TxBD) ..................................................................33-14
Port A Open-Drain Register (PAODR)......................................................................34-3
Port A Data Register (PADAT)..................................................................................34-4
Port A Data Direction Register (PADIR) ...................................................................34-4
Port A Pin Assignment Register (PAPAR).................................................................34-5
Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)......................34-6
Block Diagram for PA14 (True for all Open-Drain Port Signals)..............................34-7
Port B Open-Drain Register (PBODR).......................................................................34-8
Port B Data Register (PBDAT)...................................................................................34-9
Port B Data Direction Register (PBDIR)..................................................................34-10
Port B Pin Assignment Register (PBPAR)...............................................................34-11
Port C Data Register (PCDAT).................................................................................34-14
Port C Data Direction Register (PCDIR)..................................................................34-14
Port C Pin Assignment Register (PCPAR)...............................................................34-15
Port C Special Options Register (PCSO)..................................................................34-15