xii
MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
10.4.3
10.4.4
10.4.5
10.5
10.5.1
10.5.2
10.5.3
10.5.3.1
10.5.4
10.5.4.1
10.5.4.2
10.5.4.3
10.5.4.4
10.6
10.7
10.7.1
10.8
10.8.1
10.9
10.9.1
10.9.2
10.9.3
10.10
10.10.1
10.10.2
10.10.3
10.10.4
10.11
10.11.1
10.11.2
10.11.3
10.12
10.12.1
10.12.2
System Protection Control Register (SYPCR)...............................................10-8
Transfer Error Status Register (TESR)...........................................................10-9
Register Lock Mechanism............................................................................10-10
System Configuration.......................................................................................10-11
Interrupt Structure ........................................................................................10-11
Priority of Interrupt Sources.........................................................................10-13
SIU Interrupt Processing ..............................................................................10-14
Nonmaskable InterruptsIRQ0 and SWT ..............................................10-14
Programming the SIU Interrupt Controller ..................................................10-15
SIU Interrupt Pending Register (SIPEND) ..............................................10-15
SIU Interrupt Mask Register (SIMASK)..................................................10-16
SIU Interrupt Edge/Level Register (SIEL)...............................................10-17
SIU Interrupt Vector Register (SIVEC)...................................................10-18
The Bus Monitor...............................................................................................10-20
The Software Watchdog Timer ........................................................................10-20
Software Service Register (SWSR)..............................................................10-22
The PowerPC Decrementer..............................................................................10-22
Decrementer Register (DEC) .......................................................................10-23
The PowerPC Timebase...................................................................................10-23
Timebase Register (TBU and TBL).............................................................10-24
Timebase Reference Registers (TBREFA and TBREFB)............................10-24
Timebase Status and Control Register (TBSCR).........................................10-25
The Real-Time Clock.......................................................................................10-26
Real-Time Clock Status and Control Register (RTCSC).............................10-27
Real-Time Clock Register (RTC).................................................................10-28
Real-Time Clock Alarm Register (RTCAL)................................................10-28
Real-Time Clock Alarm Seconds Register (RTSEC) ..................................10-29
The Periodic Interrupt Timer (PIT)..................................................................10-30
Periodic Interrupt Status and Control Register (PISCR)..............................10-31
PIT Count Register (PITC)...........................................................................10-32
PIT Register (PITR) .....................................................................................10-32
General SIU Timers Operation.........................................................................10-33
Freeze Operation ..........................................................................................10-33
Low-Power Stop Operation..........................................................................10-33
Chapter 11
Reset
11.1
11.1.1
11.1.2
11.1.3
Types of Reset....................................................................................................11-1
Power-On Reset..............................................................................................11-2
External Hard Reset........................................................................................11-2
Internal Hard Reset.........................................................................................11-2