
MOTOROLA
Contents
xi
CONTENTS
Paragraph
Number
Title
Page
Number
8.8.10
8.8.11
8.8.12
8.8.12.1
8.8.12.2
8.8.12.3
8.8.12.4
8.8.12.5
8.8.13
8.9
8.10
8.10.1
8.10.1.1
8.10.2
8.10.3
8.10.4
MMU Access Protection Registers (MI_AP/MD_AP)..................................8-24
MMU Tablewalk Special Register (M_TW) .................................................8-24
MMU Debug Registers..................................................................................8-25
IMMU CAM Entry Read Register (MI_CAM).........................................8-25
IMMU RAM Entry Read Register 0 (MI_RAM0)....................................8-26
IMMU RAM Entry Read Register 1 (MI_RAM1)....................................8-27
DMMU CAM Entry Read Register (MD_CAM)......................................8-28
DMMU RAM Entry Read Register 0 (MD_RAM0).................................8-29
DMMU RAM Entry Read Register 1 (MD_RAM1).....................................8-30
Memory Management Unit Exceptions.............................................................8-32
TLB Manipulation..............................................................................................8-32
TLB Reload....................................................................................................8-32
Translation Reload Examples ....................................................................8-33
Locking TLB Entries......................................................................................8-33
Loading Locked TLB Entries.........................................................................8-34
TLB Invalidation............................................................................................8-34
Chapter 9
Instruction Execution Timing
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.2
9.2.1
9.2.2
9.2.3
Instruction Execution Timing Examples..............................................................9-1
Data Cache Load with a Data Dependency......................................................9-1
Writeback Arbitration ......................................................................................9-2
Private Writeback Bus Load ............................................................................9-3
Fastest External Load (Data Cache Miss)........................................................9-3
A Full Completion Queue................................................................................9-4
Branch Instruction Handling............................................................................9-4
Branch Prediction.............................................................................................9-5
Instruction Timing List.........................................................................................9-6
Load/Store Instruction Timing.........................................................................9-7
String Instruction Latency................................................................................9-8
Accessing Off-Core SPRs................................................................................9-8
Chapter 10
System Interface Unit
10.1
10.2
10.3
10.4
10.4.1
10.4.2
Features..............................................................................................................10-2
System Configuration and Protection ................................................................10-2
Multiplexing SIU Pins........................................................................................10-4
Programming the SIU.........................................................................................10-5
Internal Memory Map Register (IMMR).......................................................10-5
SIU Module Configuration Register (SIUMCR)...........................................10-6