參數(shù)資料
型號(hào): MCIMX507CVM8B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400
封裝: 17 X 17 MM, 0.5 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-400
文件頁數(shù): 66/120頁
文件大?。?/td> 1980K
代理商: MCIMX507CVM8B
Introduction
i.MX50 Applications Processors for Consumer Products, Rev. 0
Freescale Semiconductor
5
– USBOH1 (USB OTG and host controller complex)
– FEC Ethernet controller
MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system
and provides decode into the following slaves:
— IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and
without DMA capability
— IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and
without DMA capability
— APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its
memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing
peripheral access to many of the high-speed IP blocks on the i.MX50.
IP-Bus 3 (66 MHz)—This third peripheral bus segment contains peripherals accessible by the
ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be
accessed by the ARM CPU through IP-Bus 1 and SPBA.
Quality of service controller (QoSC)—This provides both soft and dynamic arbitration/priority
control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and
EPDC to provide dynamic priority control, based on real-time metrics.
The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption, while freeing up the CPU core for other tasks.
The i.MX50 incorporates the following hardware accelerators:
GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance
ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required
to support both LCD and EPD display applications
The i.MX50 includes the following interfaces to external devices:
NOTE
Not all the interfaces are available simultaneously depending on I/O
multiplexer configuration.
Displays:
— EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048
× 1536 at
106 Hz refresh (or 4096
× 4096 at 20 Hz)
— eLCDIF—Supporting beyond SXGA + (1400
× 1050) at 60 Hz resolutions with up to a 32-bit
display interface
— On the i.MX508, both displays can be active simultaneously. If both displays are active, the
eLCDIF only provides a 16-bit interface due to pin muxing.
Expansion cards:
— Four SD/MMC card
USB:
— One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY
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