參數(shù)資料
型號： MCIMX507CVM8B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400
封裝： 17 X 17 MM, 0.5 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-400
文件頁數(shù)： 63/120頁
文件大?。?/td> 1980K
代理商： MCIMX507CVM8B
Electrical Characteristics
i.MX50 Applications Processors for Consumer Products, Rev. 0
Freescale Semiconductor
47
4.6.5
General Purpose Media Interface (GPMI) Parameters
The i.MX50 GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to
200 MB/s I/O speed and individual chip select.
It supports Asynchronous timing mode, Source Synchronous timing mode and Samsung Toggle timing
mode separately described in the following paragraphs.
4.6.5.1
Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 8, Figure 9, Figure 10
and Figure 11 depict the relative timing between GPMI signals at the module level for different
Frequency lock time4
(FOL mode or non-integer MF)
——
—
398
Tdpdref
Phase lock time
—
100
s
Frequency jitter5 (peak value)
—
0.02
0.04
Tdck
Phase jitter (peak value)
FPL mode, integer and fractional MF
—
2.0
3.5
ns
Power dissipation
fdck =300 MHz @ avdd =1.8 V,
dvdd = 1.2 V
fdck =650 MHz @ avdd =1.8 V,
dvdd = 1.2 V
—
0.65 (avdd)
0.92 (dvdd)
1.98 (avdd)
1.8 (dvdd)
mW
1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 35.
2 The values specified here are internal to DPLL. Inside the DPLL, a 1 is added to the value specified by the user. Therefore, the
user has to enter a value 1 less than the desired value at the inputs of DPLL for PDF and MFD.
3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be
zero.
4 T
dpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
5 T
dck is the time period of the output clock, dpdck_2.
Table 36. DPLL Electrical Parameters (continued)
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX508CVK8A 制造商:Freescale Semiconductor 功能描述:CODEX 13MM W/2025D - Bulk
MCIMX508CVK8B 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX508CVK8BR2 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX508CVM8B 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX508CVM8BR2 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
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