- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45313 > MCIMX507CVM8B (FREESCALE SEMICONDUCTOR INC) SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400 PDF資料下載
參數(shù)資料
| 型號(hào)： | MCIMX507CVM8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA400 |
| 封裝： | 17 X 17 MM, 0.5 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-400 |
| 文件頁(yè)數(shù)： | 30/120頁(yè) |
| 文件大小： | 1980K |
| 代理商： | MCIMX507CVM8B |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)當(dāng)前第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
Modules List
i.MX50 Applications Processors for Consumer Products, Rev. 0
Freescale Semiconductor
17
DRAM_OPEN,
DRAM_OPENFB
(416MAPBGA and
400MAPBGA Only)
These pins are the echo gating output and feedback pins used by the DRAM PHY to bound a
window around the DQS transition. For an application using a single DRAM device, these pins
should be routed so that the
trace length (DRAM_OPEN + DRAM_OPENFB) =
trace length (DRAM_SDCLK0 + DRAM_SDQS0).
For an application using two DRAM devices, they should be routed so that the
trace length (DRAM_OPEN + DRAM_OPENFB) =
trace length (AVG(DRAM_SDCLK0+DRAM_SDCLK1) + AVG (DRAM_SDQS0_to_Device0 +
DRAM_SDQS0_to_Device1)).
This connection is required for mDDR, LPDDR2, and DDR2.
DRAM_SDODT0,
DRAM_SDODT1
(416MAPBGA and
400MAPBGA Only)
These pins are the On-die termination outputs from the i.MX50.
For DDR2, these pins should be connected to the DDR2 DRAM ODT pins. For LPDDR2 and
mDDR, these pins should be left floating. Only SDODT0 exists on the 400MAPBGA package.
DRAM_CALIBRATION
This pin is the ZQ calibration used to calibrate DRAM Ron and ODT.
For LPDDR2, this pin should be connected to ground through a 240
Ω 1% resistor. For DDR2
and LPDDR1, this pin should be connected to ground through a 300
Ω 1% resistor.
JTAG_MOD
This input has an internal 100K pull-down. Note that JTAG_MOD is referenced as SJC_MOD in
the MCIMX50 Applications Processor Reference Manual (MCIMX50RM) - both names refer to the
same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination
to GND through an external pull-down resistor (such as 1 k
Ω) is allowed.
JTAG_TCK
This input has an internal 100K pull-down. This pin is in the NVCC_JTAG domain.
JTAG_TDI
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
JTAG_TDO
This is a 3-state output with an internal gate keeper enable to prevent a floating condition. An
external pull-up or pull-down resistor on JTAG_TDO is detrimental and should be avoided. This pin
is in the NVCC_JTAG domain.
JTAG_TMS
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
JTAG_TRSTB
This input has an internal 47K pull-up to NVCC_JTAG. This pin is in the NVCC_JTAG domain.
NC
These signals are No Connect (NC) and should be floated by the user.
LOW_BATT_GPIO
If the LOW_BATT_GPIO (UART4_TXD) is asserted at power up, the i.MX50 will boot up at a lower
ARM clock frequency to reduce system power. The actual ARM clock frequency used when
LOW_BATT_GPIO is asserted is determined by the BT_LPB_FREQ[1:0] pins (220 MHz to 55.3
MHz). The polarity of the LOW_BATT_GPIO is active high by default, but may be set to active low
by setting the LOW_BATT_GPIO_LEVEL OTP bit.
See the “System Boot” chapter of the Reference Manual for more details.
Note that this is not a dedicated pin: LOW_BATT_GPIO appears on the UART4_TXD pin.
PMIC_STBY_REQ
This output may be driven high when the i.MX50 enters the STOP mode to notify the PMIC to enter
its low power standby state. This output is in the NVCC_SRTC domain.
PMIC_ON_REQ
This output from the i.MX50 can instruct the PMIC to turn on when the i.MX50 only has
NVCC_SRTC power. This may be useful for an alarm application, as it allows the i.MX50 to turn
off all blocks except for the RTC and then power on again at a specified time. This output is in the
NVCC_SRTC domain.
PMIC_RDY
This input may be used by a PMIC to signal to the i.MX50 that the PMIC supply outputs are at
operating levels when resuming from STOP mode. The PMIC_RDY input is pinmuxed on ALT3 of
the I2C3_SCL pin and is in the NVCC_MISC domain.
Table 5. Special Signal Considerations (continued)
Signal Name
Remarks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCIMX512DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX513DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX515CJM6C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX512CJM6C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
| MCIMX515DJM8C | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA529 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX508CVK8A | 制造商:Freescale Semiconductor 功能描述:CODEX 13MM W/2025D - Bulk |
| MCIMX508CVK8B | 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVK8BR2 | 功能描述:處理器 - 專門應(yīng)用 Codex 1.1 13mm RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8B | 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MCIMX508CVM8BR2 | 功能描述:處理器 - 專門應(yīng)用 Codex Rev 1.1 RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。