參數(shù)資料
型號(hào)： MC92603VF
廠商： Freescale Semiconductor
文件頁數(shù)： 92/126頁
文件大?。?/td> 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝： 1
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-MAPBGA
包裝： 托盤
Management Interface (MDIO)
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
4-12
Freescale Semiconductor
4.2.11
MDIO RA 18 (Vendor Specific)—BERT Error Counter Register
The MDIO RA 18, shown in Figure 4-10, contains the MC92603 BERT error counter register. These bits
are initially cleared to all zeros. They may be read through the MDIO interface. They are updated from the
appropriate channel’s BERT error counter when running any of the BERT tests.
8
xcvr_x_rsel
Initialized to XCVR_x_RSEL input if in redundant mode (ENAB_RED input is high). May be
written through the MDIO interface. If set indicates that data will be transmitted/received over
the secondary (redundant) links. Only applicable to Channel A and B. (R/W)
7–0
recv_error_ctr
Initialized to zero. This 8-bit counter is incremented whenever this channel’s receiver detects a
code error or disparity error. This counter is cleared when read through the MDIO interface. This
counter cannot be loaded (other than cleared) through the MDIO interface. If counter reaches
maximum value (0xFF) it will not roll over to zero; instead it will stay at this value until read. This
register is to give a quick (although not precisely accurate) reading on bit error rate.
Implementation limitations may cause some errors not to be counted. (R, SC)
1 LH = Latched high, R = read only, R/W = read and write, and SC = self-clearing.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
Reserved
BERT Error Counter Value
W
Reset
0
Figure 4-10. BERT Error Counter Register (MDIO RA 18)
Table 4-7. Channel Configuration and Status Register Field Descriptions (continued)
Bits
Name
Description1
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