參數(shù)資料
型號(hào)： MC92603VF
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 59/126頁(yè)
文件大小： 0K
描述： IC TXRX ETH QUAD GIG 256-MAPBGA
標(biāo)準(zhǔn)包裝： 1
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 4/4
規(guī)程： 千兆位以太網(wǎng)
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-MAPBGA
包裝： 托盤
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Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
3-4
Freescale Semiconductor
COMPAT
IEEE Std. 802.3-2002
compatibility mode enable
Indicates that the receiver is in a IEEE Std.
802.3-2002 compliant mode. If code group
addition/deletion is required to maintain alignment,
then special rules are followed that non-intrusive to
the IEEE Std. 802.3-2002 packet streams. See
Data Streams,” for more information.
Input
High
XCVR_x_LBE
Enable loopback
Indicates that data into the receiver is to be taken
from the corresponding transmitter.
Input
High
DROP_SYNC
Drop synchronization
DROP_SYNC may be used with
XCVR_x_DISABLE to force a receiver to resync, but
it does not affect the transmitter operation.
Input
High
RCCE
Recovered clock enable
Indicates that the output data is synchronized to a
recovered clock.
Input
High
ADIE
Add/delete idle enable
Indicates that the receiver is free to add/delete code
groups to/from the output data stream to maintain
information. This input is ignored if RCCE is high.
Input
High
TBIE
Ten-bit interface enable
Indicates that the receiver interface is in a 10-bit
mode, and that the 8B/10B decoder is bypassed.
Input
High
HSE
Half-speed enable
Indicates that the link and data interfaces are to be
operated at half-speed.
Input
High
REPE
Repeater mode enable
Causes data received to be transmitted over the
corresponding transmit channel. See Section 5.5,
“Repeater Mode,” for details.
Input
High
ENAB_RED
Enable redundant mode
Enable redundant link operation.
Input
High
XCVR_x_RSEL
Select redundant channel
Receive data from secondary (redundant) channel.
Input
High
MEDIA
Media impedance select
Indicates the impedance of the transmission media.
When the MEDIA signal is negated low, it indicates
50
and when asserted high, it indicates 75 .
Input
—
RECV_CLK_CENT
Center recovered clock
Indicates that the recovered clocks
(RECV_x_RCLK and RECV_x_RCLK_B) will be
centered relative to the receive data and status
outputs.
Input
High
TST_0/TST_1
Test mode
Indicates the operating/test mode of the device.
Input
—
REF_CLK_P/N
PLL reference clock
PLL reference clock input. The signal also provides
reference frequency for the receiver interface when
recovered clock mode is disabled (RCCE is low).
Input
—
RLINK_x_N/
RLINK_x_P
Link serial receive data
Differential serial receive data input pads
Input
—
Internal Signals
rx_clock
High-speed clock
Internal, differential high speed clock, used to
transmit and receive link data.
Input
—
loop_back_data
Loopback data
Differential loopback receive data
Input
—
repeat_data
Repeater data
Data received that is looped to the transmitter if in
repeater mode (REPE is asserted high). Test
feature only.
Output
—
Table 3-1. MC92603 Receiver Interface Signals (continued)
Signal Name
Description
Function
Direction
Active
State
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