參數(shù)資料
型號(hào): MC92604VM
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 0K
描述: IC ETH TXRX DUAL GIG 196-MAPBGA
標(biāo)準(zhǔn)包裝: 630
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: 千兆位以太網(wǎng)
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 196-LBGA
供應(yīng)商設(shè)備封裝: 196-MAPBGA(15x15)
包裝: 托盤(pán)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Overview
This document explains the basic fundamental features and functional operation of the
MC92603 Quad and MC92604 Dual Gigabit Ethernet transceivers (GEt). The MC92603 is a
quad device and each channel may be operated independently or in a ‘trunking’, word aligned,
mode. The MC92604 is a two channel version and is offered in a smaller package. Although
the remainder of this document discusses the MC92603, the attributes are the same for the
MC92604.
The Gigabit Ethernet transceiver was designed with the intent to meet the requirements of
IEEE Std 802.3-2002. It was designed to fully support full-duplex GMII or TBI PHY
applications including the reduced RGMII or RTBI de facto interfaces. Each channel also has
its own independent MDIO register set as specied in the above standard
The MC92603 GEt is designed as two parts in one. It may be congured as either a 1 gigabit
backplane SERDES functionally similar to the MC92600, 1.25 Gbaud Quad SERDES, or as
a quad 1 gigabit Ethernet GMII or TBI PHY.
The GEt is a high-speed, full-duplex, serial data interface device that can be used to transmit
data between chips across a board, through a backplane, or through cabling, as well as to
interface to GBIC/SFP modules. The multi-channel devices have transceivers that transmit
and receive coded data at a rate of 1.0 Gbps through each 1.25 gigabaud link.
The MC92603 is built upon the proven transceiver technology of the MC92600 and MC92602
devices. Carefully designed for low power consumption, its 0.25 micron CMOS
implementation nominally consumes less than 1 W with all links operating at full speed when
in the backplane interface mode.
The MC92603 features transmit FIFOs and source synchronous transmit clocks per channel
to further simplify interfacing. And nally, IEEE Std 1149.1 JTAG boundary scan is added
for board test support.
Features
The MC92603 and MC92604 have two applications oriented operating modes depending
upon conguration. It may be used as a backplane SERDES or as an Ethernet PHY.
Product Brief
MC92603PB/D
Rev. 0, 3/2003
MC92603 Quad and
MC92604 Dual
Gigabit Ethernet
Transceivers
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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