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| 型號： | MC92603VF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 60/126頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-MAPBGA |
| 包裝： | 托盤 |
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Receiver
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
3-5
3.3
Functional Description
The MC92603 receiver receives differential data in one of two operating ranges. It may be operated in full
rate range with a maximum data rate of 1.0 Gbps (1.25 Gigabaud) or at half-rate at
500 Mbps (0.625 Gigabaud). The operating range is determined by the state of the HSE input and the
frequency of the reference clock, see Table 5-1.
Transmitted data is recovered using an oversampled transition tracking method. The received serial data
is accumulated into 10-bit characters. The 10-bit characters are forwarded to the 8B/10B decoder where
the original data is obtained. Alternately, the decoder can be bypassed, and the 10-bit character is
forwarded to the receiver interface in the 10-bit interface (TBI) mode.
The receiver provides for byte (character) alignment. Alignment assures that the byte, presented at the
input of the transmitter is preserved when it is presented by the receiver. Optionally, alignment may be
disabled if in the backplane 10- or 5-bit mode.
The code group alignment is obtained by aligning to COMMA (K28.1, K28.5, or K28.7) code groups.
Alignment is achieved when four COMMA code groups with the same alignment, are detected.
NOTE
The COMMA code group (K28.7) should be used carefully since the
combination of this code group with some adjoining code groups will yield
false COMMA alignment.
The receiver also provides for word synchronization (this feature is available only in ‘backplane’ operating
modes). In this mode, all of the receivers are being used cooperatively to receive 32-bit (40-bit in TBI
mode) words. Word synchronization ensures that the receivers present the 4 bytes of a word
simultaneously.
At the receiver interface is where the received bytes and status codes are obtained. The receiver interface
has several modes of operation and timing that allow it to be used in a variety of applications. The
following sections provide a detailed description of the receiver and its modes of operation.
3.3.1
Input Amplifier
The input amplifiers connect directly to the link input pads RLINK_x_P and RLINK_x_N. It is a
differential amplifier with an integrated analog multiplexer for loopback testing. Link termination resistors
are integrated with the amplifier. The termination resistance is either 100 or 150
differential depending
on the state of the MEDIA configuration input pin. Termination resistance is 100
(differential) when the
MEDIA is low and 150
(differential) when the MEDIA is high.
The input amplifier facilitates a loopback path for production and in-system testing. When the MC92603
is in loopback mode (loopback enable, LBE, is high), the input amplifier selects the loopback differential
input signals and ignores the state on the RLINK_x_P and RLINK_x_N signals. This allows in-system
information on test modes.
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