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| 型號(hào)： | MC92603VF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 91/126頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETH QUAD GIG 256-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-MAPBGA |
| 包裝： | 托盤 |
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Management Interface (MDIO)
MC92603 Quad Gigabit Ethernet Transceiver Reference Manual, Rev. 1
Freescale Semiconductor
4-11
4.2.10
MDIO RA 17 (Vendor Specific)—Channel Configuration and Status
Register
MDIO RA 17 contains the MC92603 channel configuration and status register. These bits are initially
loaded on power up from the corresponding states of the external MC92603 configuration input pins. They
may be modified through the MDIO interface. It is not necessary to reset the device logic if these bits are
modified. Figure 4-9 shows the content of register 17.
Table 4-7 lists the corresponding field descriptions for the channel configuration and status register.
15
14
13
12
11
10
9
8
R
m_xcvr_
disable
i_xcvr_
disable
overrun
underrun
an_mode
recv_clk_cent
broadcast_
mode
xcvr_x_rsel
W
Reset
0
XCVR_x_
DISABLE
0
RECV_CLK_
CENT
BROADCAST
XCVR_x_
RSEL
7
6
5
4
3
2
1
0
R
Receiver Error Counter
W
Reset
0
Figure 4-9. Channel Configuration and Status Register (MDIO RA 17)
Table 4-7. Channel Configuration and Status Register Field Descriptions
Bits
Name
Description1
15
m_xcvr_disable
Initialized to zero. May be written through the MDIO interface. A software disable, when set
indicates that channel is to be disabled to reduce power. The channel is disabled if either bit 15
or 14 are set. (R/W)
14
i_xcvr_x_disable
Contains the value of the XCVR_x_DISABLE input. (R)
13
overrun
Bit 13 is initialized to zero and then is set to one only if this channel ‘overruns’ due to clock
mismatch between the transmitter and receiver. Once set this bit is ‘sticky.’ That is, it remains
set until register 17 is read through the MDIO interface. This bit may not be written through the
MDIO interface. (R, LH, SC)
12
underrun
Bit 12 is initialized to zero and then is set to one only if this channel ‘underrun’ due to clock
mismatch between the transmitter and receiver. Once set this bit is ‘sticky.’ That is, it remains
set until register 17 is read through the MDIO interface. This bit may not be written through the
MDIO interface. (R, LH, SC)
11
an_mode
Initialized to zero. This bit is set whenever this channel’s transmitter is in the auto-negotiation
mode. This bit may not be written through the MDIO interface. (R)
10
recv_clk_cent
Initialized to RECV_CLK_CENT input. May be written through the MDIO interface. If set,
indicates that data out of the receiver is centered relative to the RECV_x_RCLK output. (R/W)
9
broadcast
Initialized to BROADCAST input if in redundant mode (ENAB_RED input is high). May be written
through the MDIO interface if in redundant mode. If set indicates that data will be transmitted
over both of the transmit links. Only applicable to Channel A and B. (R/W)
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