參數(shù)資料
型號: MC92600
廠商: Motorola, Inc.
英文描述: High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述: 高速,全雙工,串行數(shù)據(jù)接口(高速全雙工串行數(shù)據(jù)接口)
文件頁數(shù): 68/82頁
文件大?。?/td> 1056K
代理商: MC92600
6-22
MC92600 WarpLink Quad Users Manual
WarpLink Quad Chip Pinout Listing
RECV_C_RCLK
Receiver C, receive data clock
G1
H1
Output
TTL
RLINK_C_P
Receiver C, positive link input
E14
G17
Input
Link
RLINK_C_N
Receiver C, negative link input
F14
H17
Input
Link
XLINK_C_P
Transmitter C, positive link out
E11
G14
Output
Link
XLINK_C_N
Transmitter C, negative link out
F11
H14
Output
Link
XMIT_D_0
Transmitter D, data bit 0
D8
C10
Input
TTL
XMIT_D_1
Transmitter D, data bit 1
C8
C11
Input
TTL
XMIT_D_2
Transmitter D, data bit 2
A8
A11
Input
TTL
XMIT_D_3
Transmitter D, data bit 3
B8
B11
Input
TTL
XMIT_D_4
Transmitter D, data bit 4
D9
A12
Input
TTL
XMIT_D_5
Transmitter D, data bit 5
A9
B12
Input
TTL
XMIT_D_6
Transmitter D, data bit 6
B9
C13
Input
TTL
XMIT_D_7
Transmitter D, data bit 7
A10
A13
Input
TTL
XMIT_D_K
Transmitter D, special character
(data bit 8 for TBI mode)
B10
B13
Input
TTL
XMIT_D_IDLE_B
Transmitter D, idle enable bar,
(data bit 9 for TBI mode)
E9
D13
Input
TTL
RECV_D_0
Receiver D, data bit 0
D3
D2
Output
TTL
RECV_D_1
Receiver D, data bit 1
E4
C3
Output
TTL
RECV_D_2
Receiver D, data bit 2
B1
C1
Output
TTL
RECV_D_3
Receiver D, data bit 3
C2
B1
Output
TTL
RECV_D_4
Receiver D, data bit 4
A1
C2
Output
TTL
RECV_D_5
Receiver D, data bit 5
C5
B3
Output
TTL
RECV_D_6
Receiver D, data bit 6
C3
A3
Output
TTL
RECV_D_7
Receiver D, data bit 7
C4
B4
Output
TTL
RECV_D_K
Receiver D, special character
(data bit 8 for TBI mode)
A2
C4
Output
TTL
RECV_D_9
Receiver D, data bit 9 for TBI
mode
B3
C5
Output
TTL
RECV_D_IDLE
Receiver D, idle detect
D5
B5
Output
TTL
RECV_D_ERR
Receiver D, error detect
A4
C6
Output
TTL
RECV_D_RCLK
Receiver D, receive data clock
A3
A4
Output
TTL
RLINK_D_P
Receiver D, positive link input
C14
E17
Input
Link
RLINK_D_N
Receiver D, negative link input
B14
D17
Input
Link
XLINK_D_P
Transmitter D, positive link out
E12
G15
Output
Link
XLINK_D_N
Transmitter D, negative link out
D12
F15
Output
Link
TBIE
10-bit interface enable
N12
T15
Input
TTL
Table 6-16. WarpLink Quad Chip Pinout List (Continued)
Signal Name
Description
Ball Number
(196 FBGA)
Ball Number
(217 PBGA)
Direction
I/O Type
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