參數(shù)資料
型號(hào): MC92600
廠商: Motorola, Inc.
英文描述: High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述: 高速,全雙工,串行數(shù)據(jù)接口(高速全雙工串行數(shù)據(jù)接口)
文件頁數(shù): 58/82頁
文件大?。?/td> 1056K
代理商: MC92600
6-12
MC92600 WarpLink Quad Users Manual
Package Description
A 1uF ceramic chip capacitor should exist on each side of the WarpLink Quad
device. This should be done for both the 1.8V supply and the 3.3V supply.
Between the WarpLink Quad device and the voltage regulator should be a 10uF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor, and a 100uF, low
ESR SMT tantalum chip capacitor. This should be done for both the 1.8V supply and
the 3.3V supply.
6.2 Package Description
This section provides the package parameters and mechanical dimensions of the MC92600
WarpLink Quad device.
The WarpLink Quad is offered in two packages, a 196 FBGA and a 217 PBGA. The 196
FBGA utilizes an aggressive 1 mm ball pitch and 15 mm body size for application where
board space is limited. The 217 PBGA utilizes a standard 1.27 mm ball pitch and 23 mm
body size that eases board routing.
6.2.1 196 FBGA Package Parameter Summary
Package Type:
Package Outline:
Package Height:
Number of Balls:
Ball Pitch:
Ball Diameter:
Fine pitch ball grid array
15 mm x 15 mm
1.75 mm Max
196
1 mm
0.35D0.65 mm
6.2.2 217 PBGA Package Parameter Summary
Package Type:
Package Outline:
Package Height:
Number of Balls:
Ball Pitch:
Ball Diameter:
Plastic ball grid array
23 mm x 23 mm
2.32 mm Max
217
1.27 mm
0.60D0.90 mm
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