參數(shù)資料
型號(hào)： MC92600
廠商： Motorola, Inc.
英文描述： High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述： 高速，全雙工，串行數(shù)據(jù)接口（高速全雙工串行數(shù)據(jù)接口）
文件頁數(shù)： 18/82頁
文件大?。?/td> 1056K
代理商： MC92600
2-4
MC92600 WarpLink Quad Users Manual
Transmission Modes
2.3 Transmission Modes
WarpLink accepts two transmission modes: double data rate mode and repeater mode.
2.3.1 Double Data Rate Mode
Double data rate (DDR) mode enables sampling and storage of the data inputs to the
transmitter on the rising and falling edges of REF_CLK. Data is placed in the transmit data
input register. DDR mode is used to lower reference clock frequency while maintaining
throughput, reducing board design complications. Table 3-5, "Legal Reference Clock
Frequency Rangesó shows legal reference clock frequencies for all modes of operation.
DDR mode is enabled by asserting DDRE.
2.3.2 Repeater Mode
Repeater mode conTgures the WarpLink Quad into a 4-link receive-transmit repeater so
that data can enter serially and exit serially. In this mode, the data to transmit is obtained
from its receiver (transmitter A gets receiver As data, transmitter B gets receiver Bs data,
and so on). The transmit input signals, XMIT_n_7 through XMIT_n_0, XMIT_n_K, and
XMIT_n_IDLE_B are ignored. Repeater mode is enabled by setting REPE high.
In repeater mode transmit data is sampled and stored in the transmit data input register on
the rising edge of the reference clock (REF_CLK). See Section 3.5.4.5, òRepeater Modeó
for more information on repeater mode.
REF_CLK
Reference clock
System reference clock to which the
transmit interfaces are timed.
Frequency requirement is dependent
on HSE and DDRE settings. See
Section 3.6, òReference Clock
Frequenciesó and Table 3-5 for
conTguration options.
Input
MEDIA
Media impedance
select
Indicates the impedance of the
transmission media. Low indicates
50
W
and high indicates 75
W
.
Input
XLINK_n_N/
XLINK_n_P
Link serial transmit data
Differential serial transmit data output
pads.
Output
Internal Signals
rx_clock
High speed transceiver
clock
Internal, differential high-speed clock
used to transmit and receive link data.
Input
repeat_data
Received repeat data
Repeater mode, received data to
retransmit.
Input
loop_back_data
Loop back data
Differential loop back transmit data.
Output
Table 2-1. WarpLink Quad Transmitter Interface Signals (Continued)
Signal Name
Description
Function
Direction
Active
State
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