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參數資料
| 型號： | MC92600 |
| 廠商： | Motorola, Inc. |
| 英文描述： | High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數據接口) |
| 中文描述： | 高速，全雙工，串行數據接口（高速全雙工串行數據接口） |
| 文件頁數： | 35/82頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | MC92600 |
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Chapter 3. WarpLink Receiver
3-13
Device Operations
The receiver interface is timed to the recovered clock, RECV_n_RCLK, or to the reference
clock, REF_CLK, depending on the state of the RCCE signal.
3.5.4.2 10-Bit Interface Mode
Received data is ten bits of coded data when in TBI mode. The internal 8B/10B decoder is
not used, and it is assumed that decoding is done externally. 10-bit data is made up from the
collection of signals RECV_n_9, RECV_n_K, and RECV_n_7 through RECV_n_0
making up bits 9 through 0, respectively. 10-bit interface mode is enabled by setting the
TBIE signal high.
The RECV_n_IDLE is asserted when the 10-bit character is the special 8B/10B idle
(K28.5) code. This can be used by system logic for synchronization or data parsing.
RECV_n_IDLE is set low when the data is normal data or a non-idle special code.
The RECV_n_ERR is set low when the receiver is operating normally, and is asserted when
the receiver is in an error state. The state of the RECV_n_IDLE signal is decoded to
determine the error condition. Table 3-7 describes the error codes and their meaning.
The receiver interface is timed to the recovered clock, RECV_n_RCLK, or to the reference
clock, REF_CLK, depending on the state of the RCCE signal.
3.5.4.3 Double Data Rate Mode
Double data rate (DDR) mode, enabled when DDRE is asserted, allows the received data
to be output on the rising
and
falling edges of a reference or recovered clock. DDR mode
is used to lower reference clock frequency while maintaining throughput, reducing board
design complications. It is important to note that in DDR mode the legal range of reference
clock frequencies is reduced. Table 3-5, "Legal Reference Clock Frequency Rangesó shows
legal reference clock frequencies for all modes of operation.
3.5.4.4 Half-Speed Mode
Half-speed (HS) mode, enabled when HSE is asserted, operates the receiver in its lower
speed range. In HS mode, the link speed is 500 Mbps (625 Mbaud.) The receiver interface
operates at half speed as well, in pace with received data.
3.5.4.5 Repeater Mode
Repeater mode conTgures the WarpLink Quad into a 4-link receive-transmit repeater. In
this mode, received data is forwarded to the transmitter for re-transmission. Link As
receiver forwards to link As transmitter, link Bs receiver to link Bs transmitter, and so on.
The receivers data outputs and status signals reect the received data and the current status
of the receiver. See Section 2.3.2, òRepeater Modeó for more information on repeater
mode.
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