參數(shù)資料
型號: MC92600
廠商: Motorola, Inc.
英文描述: High-speed, Full-duplex, Serial Data Interface(高速全雙工串行數(shù)據(jù)接口)
中文描述: 高速,全雙工,串行數(shù)據(jù)接口(高速全雙工串行數(shù)據(jù)接口)
文件頁數(shù): 24/82頁
文件大?。?/td> 1056K
代理商: MC92600
3-2
MC92600 WarpLink Quad Users Manual
WarpLink Receiver Block Diagram
3.1 WarpLink Receiver Block Diagram
Figure 3-1. WarpLink Receiver Block Diagram
3.2 WarpLink Receiver Interface Signals
This section describes the interface signals of the WarpLink Quad receiver. Each signal is
described, including its name, function, direction and active state in Table 3-1. The tables
signal names use the letter ònó as a place holder for links òAó through òDó. Internal signals
are not available at the I/O of the device, but are presented to illustrate device operation.
Delay Line,
16 Samples
RECV
Amp
loop_back_data
RECV_n_K
RCCE
REF_CLK
WSE
XMIT_n_K
WSE_GEN
BSYNC_1
RLINK_n_N
MEDIA
RLINK_n_P
HSE
Idle Detection &
Byte Alignment
Data Recovery
8B/10B
Decoder
Alignment
FIFO
BIST/BERT
Analyzer
Word Alignment
drop/add
DDRE
ADIE
RECV_n_[7:0]
RECV_n_9
RECV_n_IDLE
repeat_data
REPE
Receiver
Interface
over_underrun
TST_1
TST_0
TBIE
rx_clock
RECV_n_ERR
RECV_n_RCL
recv_byte_clock
idle_detect
Transition Tracking Loop &
BSYNC_0
Timing Alignment
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