參數(shù)資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 94/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MOTOROLA
94
MC68HC916X1
MC68HC916X1TS/D
IPL[2:0] — Interrupt Priority Level
This field specifies the priority level of interrupts generated by the GPT.
IVBA[3:0] — Interrupt Vector Base Address
Most significant nibble of interrupt vector numbers generated by the GPT. Refer to
Table 45
.
When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and
PORTGP holds the 8-bit data.
DDRGP[7:0] — Port GP Data Direction Register
0 = Input only
1 = Output
All OC outputs can be controlled by the action of OC1. OC1M contains a mask that determines
which pins are affected. OC1D determines what the outputs are.
OC1M[5:1] — OC1 Mask Field
0 = Corresponding output compare pin is not affected by OC1 compare.
1 = Corresponding output compare pin is affected by OC1 compare.
OC1M[5:1] correspond to OC[5:1].
OC1D[5:1] — OC1 Data Field
0 = If OC1 mask bit is set, clear the corresponding output compare pin on OC1 match.
1 = If OC1 mask bit is set, set the corresponding output compare pin on OC1 match.
OC1D[5:1] correspond to OC[5:1].
Table 45 GPT Interrupt Sources
Name
—
IC1
IC2
IC3
OC1
OC2
OC3
OC4
IC4/OC5
TO
PAOV
PAI
Source Number
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Source
Vector Number
IVBA : 0000
IVBA : 0001
IVBA : 0010
IVBA : 0011
IVBA : 0100
IVBA : 0101
IVBA : 0110
IVBA : 0111
IVBA : 1000
IVBA : 1001
IVBA : 1010
IVBA : 1011
Adjusted Channel
Input Capture 1
Input Capture 2
Input Capture 3
Output Compare 1
Output Compare 2
Output Compare 3
Output Compare 4
Input Capture 4/Output Compare 5
Timer Overflow
Pulse Accumulator Overflow
Pulse Accumulator Input
DDRGP/PORTGP
— Port GP Data Direction Register/Port GP Data Register
$YFF906
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDRGP
PORTGP
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC1M/OC1D
— OC1 Action Mask Register/OC1 Action Data Register
$YFF908
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OC1M[5:1]
0
0
0
OC1D[5:1]
0
0
0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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