參數(shù)資料
型號: MC68HC916X1
廠商: Motorola, Inc.
英文描述: 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述: 16位微控制器模塊(16位模塊化微控制器)
文件頁數(shù): 27/172頁
文件大小: 1035K
代理商: MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
27
SWT[1:0] — Software Watchdog Timing
This field selects the divide ratio used to establish software watchdog time-out period.
Table 15
gives
the ratio for each combination of SWP and SWT bits.
HME — Halt Monitor Enable
0 = Disable halt monitor function
1 = Enable halt monitor function
BME — Bus Monitor Enable
0 = Disable bus monitor function for internal to external bus cycles.
1 = Enable bus monitor function for internal to external bus cycles.
BMT[1:0] — Bus Monitor Timing
This field selects a bus monitor time-out period as shown in
Table 16
.
3.4.1 Bus Monitor
The internal bus monitor checks for excessively long response times during normal bus cycles
(DSACK1) and during IACK cycles. The monitor asserts the internal BERR signal if response time
is excessive.
DSACK1 response times are measured in clock cycles. The maximum allowable response time can
be selected by setting BMT[1:0].
The monitor does not check DSACK1 response on the external bus unless the CPU16 initiates the
bus cycle. The BME bit in SYPCR enables the internal bus monitor for internal to external bus cy-
cles. If a system contains external bus masters, an external bus monitor must be implemented, and
the internal to external bus monitor option must be disabled.
Table 15 Software Watchdog Timeout Period Divide Ratio
SWP
0
SWT[1:0]
00
Ratio
2
9
2
11
2
13
2
15
2
18
2
20
2
22
2
24
0
01
0
10
0
11
1
00
1
01
1
10
1
11
Table 16 Bus Monitor Timeout Period
BMT[1:0]
0 0
0 1
1 0
1 1
Time-Out
64 System Clocks
32 System Clocks
16 System Clocks
8 System Clocks
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