參數(shù)資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 41/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
41
ADDR[23:11] — Base Address Field
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to ad-
dress lines.
Since ADDR20 = ADDR19 in the CPU16, the maximum block size is 512 Kbytes. Because AD-
DR[23:20] follow the logic state of ADDR19, if all 24 address lines are used, addresses from $080000
to $F7FFFF are inaccessible.
BLKSZ[2:0] — Block Size Field
This field determines the size of the block above the base address that must be enabled by the chip
select.
Table 25
shows bit encoding for the base address registers block size field.
3.9.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip
select signals. These make the chip selects useful for generating peripheral control signals. Certain
constraints set by fields in the base address register and in the option register must be satisfied to
assert a chip select signal and to provide DSACK or autovector support.
NOTE
CSBOOT is not present on the MC68HC916X1, however, the CSBOOT chip-select
logic is still present and should be disabled before other chip-selects are initialized.
1. During normal operation ADDR[23:20] is at the same logic level as
ADDR19.
Table 25 Block Size Field Bit Encoding
BLKSZ[2:0]
000
001
010
011
100
101
110
111
Block Size
2 K
8 K
16 K
64 K
128 K
256 K
512 K
512 K
Address Lines Compared
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
1
CSORBT
— Chip-Select Option Register Boot ROM
$YFFA4A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE[2:0]
R/
W
[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
1
1
1
1
0
1
1
0
1
1
1
0
0
0
0
CSOR[0:10]
— Chip-Select Option Registers
$YFFA4E–YFFA76
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE[1:0]
R/
W
[1:0]
STRB
DSACK[3:0]
SPACE[1:0]
IPL[2:0]
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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