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參數(shù)資料
| 型號(hào)： | MC68HC916X1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁(yè)數(shù)： | 136/172頁(yè) |
| 文件大?。?/td> | 1035K |
| 代理商： | MC68HC916X1 |
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MOTOROLA
136
MC68HC916X1
MC68HC916X1TS/D
BFEBAH and BFEBAL contain the 13 high-order bits of the BEFLASH array base address. During
reset, BFEBAH and BFEBAL take on the default values programmed into the associated shadow
registers. After reset, if LOCK = 0 and STOP = 1, software can write to BFEBAH and BFEBAL to
relocate the BEFLASH array. Because the states of ADDR[23:20] follow the state of ADDR19, ad-
dresses in the range $080000 to $F7FFFF cannot be accessed by the CPU16. If the BEFLASH ar-
ray is mapped to these addresses, the system must be reset before the array can be accessed.
BFECTL contains the bits needed to control programming and erasing the BEFLASH.
VFPE — Verify Program/Erase
0 = Normal read cycles
1 = Invoke program-verify circuit
This bit invokes a special program-verify circuit. During programming sequences (ERAS = 0), VFPE is
used in conjunction with the LAT bit to determine when programming of a location is complete. If VFPE
and LAT are both set, a bit-wise exclusive-OR of the latched data with the data in the location being
programmed occurs when any valid BEFLASH location is read. If the location is completely pro-
grammed, a value of zero is read. Any other value indicates that the location is not fully programmed.
When VFPE is cleared, normal reads of valid BEFLASH locations occur.
ERAS — Erase Control
0 = BEFLASH configured for programming
1 = BEFLASH configured for erasure
The ERAS bit in BFECTL configures the BEFLASH array for programming or erasure. Setting ERAS
causes all locations in the array and all BEFLASH shadow bits in the control block to be configured for
erasure.
Table 71
shows the address ranges that must be written to during an erase operation in order
to erase specific blocks of the BEFLASH array.
1. The block erasable flash base address high and low registers (BFEBAH and BFEBAL) specify ADDR[23:11] of
the block to be erased.
2. These address bits are “don’t cares” when specifying the block to be erased.
3. Erasing the entire array also erases the BEFLASH control register shadow bits.
BFECTL
— BEFLASH Control Register
$YFF7A8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
VFPE
ERAS
LAT
ENPE
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 71 BEFLASH Erase Operation Address Ranges
Block
Addresses
Affected
Address Bits Used to Specify Block for Erasure
ADDR[10:6]
ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
X
ADDR[23:11]
0
1
2
3
4
5
6
7
$0000 – $007F
$0080 – $0100
$0100 – $017F
$0180 – $01FF
$0200 – $02FF
$0300 – $03FF
$0400 – $05FF
$0600 – $07FF
Reserved
$0600 – $07FF
BFEBAH/
BFEBAL
1
X
2
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
X
X
2
Entire
Array
3
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