參數(shù)資料
型號： MC68HC916X1
廠商： Motorola, Inc.
英文描述： 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述： 16位微控制器模塊（16位模塊化微控制器）
文件頁數(shù)： 40/172頁
文件大?。?/td> 1035K
代理商： MC68HC916X1
MOTOROLA
40
MC68HC916X1
MC68HC916X1TS/D
A pin programmed as a discrete output drives an external signal to the value specified in the port C
data register (PORTC), with the following exceptions:
No discrete output function is available on pins BR, BG, or BGACK.
ADDR23 provides ECLK output rather than a discrete output signal.
Internal chip select logic is inhibited when discrete output or alternate function are assigned.
Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit
port, the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16-
bit port, the upper/lower byte field of the option register selects the byte with which the chip select
is associated.
3.9.3 Base Address Registers
A base address is the starting address for the block enabled by a given chip select. Block size de-
termines the extent of the block above the base address. Each chip select has an associated base
register so that an efficient address map can be constructed for each application. If a chip select is
assigned an address used by a microcontroller module, the module has priority. The chip select
does not respond to an access.
ADDR[23:20] is at the same logic level as ADDR19 during internal CPU master operation. AD-
DR[23:20] must match ADDR19 for the chip select to be active.
NOTE
CSBOOT is not present on the MC68HC916X1, however, the CSBOOT chip-select
logic is still present and should be disabled before other chip-selects are initialized.
Table 24 CSPAR1 Pin Functions
CSPAR1 Field
CSPA1[9:8]
CSPA1[7:6]
CSPA1[5:4]
CSPA1[3:2]
CSPA1[1:0]
Chip-Select Signal
CS10
—
—
—
CS6
Alternate Signal
ADDR23
—
—
—
ADDR19
Discrete Output
ECLK
—
—
—
PC3
CSBARBT
— Chip-Select Base Address Register Boot ROM
$YFFA48
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
BLKSZ[2:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
CSBAR[0:10]
— Chip-Select Base Address Registers
$YFFA4C–$YFFA74
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
BLKSZ[2:0]
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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