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參數(shù)資料
| 型號(hào)： | MC68HC916X1 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 16-Bit Modular Microcontroller(16位模塊化微控制器) |
| 中文描述： | 16位微控制器模塊（16位模塊化微控制器） |
| 文件頁(yè)數(shù)： | 113/172頁(yè) |
| 文件大?。?/td> | 1035K |
| 代理商： | MC68HC916X1 |
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MC68HC916X1
MC68HC916X1TS/D
MOTOROLA
113
Command RAM is used by the QSPI when in master mode. The CPU writes one byte of control
information to this segment for each QSPI command to be executed. The QSPI cannot modify in-
formation in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select
field enables peripherals for transfer. The command control field provides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from
the address in NEWQP[3:0] through the address in ENDQP[3:0]. (Both of these fields are in
SPCR2).
CONT — Continue
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete.
BITSE — Bits per Transfer Enable
0 = 8 bits
1 = Number of bits set in BITS[3:0] field of SPCR0
DT — Delay after Transfer
The QSPI provides a variable delay at the end of serial transfer to facilitate the interface with peripherals
that have a latency requirement. The delay between transfers is determined by the SPCR1 DTL[6:0]
field.
DSCK — PCS to SCK Delay
0 = PCS valid to SCK transition is one-half SCK.
1 = SPCR1 DSCKL[6:0] field specifies delay from PCS valid to SCK.
PCS[3:0] — Peripheral Chip Select
Use peripheral chip-select bits to select an external device for serial data transfer. More than one pe-
ripheral chip select can be activated at a time, and more than one peripheral chip can be connected to
each PCS pin, provided that proper fanout is observed.
7.4.4 Operating Modes
The QSPI operates in either master or slave mode. Master mode is used when the MCU originates
data transfers. Slave mode is used when an external device initiates serial transfers to the MCU
through the QSPI. Switching between the modes is controlled by MSTR in SPCR0. Before entering
either mode, appropriate QSM and QSPI registers must be properly initialized.
1.
The PCS0 bit represents the dual-function PCS0/SS
.
CR[0:F]
— Command RAM
$YFFD40
7
6
5
4
3
2
1
0
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0
1
–
–
–
–
–
–
–
–
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0
1
COMMAND CONTROL
PERIPHERAL CHIP SELECT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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