參數(shù)資料
型號(hào)： MC68HC705CL4FU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 70/101頁(yè)
文件大?。?/td> 517K
代理商： MC68HC705CL4FU
GENERAL RELEASE SPECIFICATION
February 12, 1997
MOTOROLA
CALLER ID
MC68HC05CL4
10-6
REV 2.0
10.2.2 Control/status register 2 (CLCSR2)
CD—Carrier Detect
This read only bit returns the value of the Carrier Detect signal which goes low
when a valid carrier is detected and remains low while the carrier remains valid.
RD—Ring Detect
This read only bit returns the value of the Ring Detect signal which goes low
when a valid ringing signal is detected and remains low as long as the ringing
signal remains valid.
CIDSD—Caller ID Serial Data
This read only bit returns the value of the Caller ID Serial Data (output of the on
chip demodulator) whenever the CD is low. This data includes the alternate 0
and 1 pattern, 150 ms marking which precedes the data. At all other times the
demodulator output is high. The source of this data bit is selected by bit 7 in this
register.
CDPW—Carrier Detect Power Up
Carrier detection is enabled when this bit is set. An interrupt will be generated
when a valid carrier is detected provided the CDIE bit in the CLCSR1 register is
set.
RDPW—Ring Detect Power Up
Ring detection is enabled when this bit is set. An interrupt will be generated
when a valid ring is detected provided the RDIE bit in the CLCSR1 register is
set.
10.2.3 Control/status register 3 (CLCSR3)
CDOE - Carrier Detect Override Enable
Setting this bit allows the user to force the carrier detect signal by writing a zero
to CDO, bit 0 in the CLCSR1 register.
76543210
REG
$000D
READ
RDPW
CDPW
CIDSD
RD
CD
WRITE
RESET
U
0
UUUUU
U = UNAFFECTED
76543210
REG
$000D
READ
SDSL
RDEDG
CDEDG
RDOE
CDOE
WRITE
RESET
0
U
0000
U = UNAFFECTED
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參數(shù)描述
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