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參數(shù)資料
| 型號(hào)： | MC68HC705CL4FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 31/101頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | MC68HC705CL4FU |
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February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
LOW POWER MODES
MOTOROLA
REV 2.0
6-1
SECTION 6
LOW POWER MODES
The MC68HC05CL4 has two low-power operational modes. The WAIT and STOP
instructions provide two modes that reduce the power required for the MCU by
stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP Watchdog Timer is enabled. The
ow of the STOP and WAIT modes is shown in Figure 6-1.
6.1
STOP INSTRUCTION
Execution of the STOP instruction, places the MCU in its lowest power consump-
tion mode. In the STOP Mode the internal oscillator is turned off, halting
all inter-
nal processing, including the COP Watchdog Timer.
When the CPU enters STOP Mode the I-bit in the Condition Code Register will be
cleared automatically, so that any hardware interrupt (IRQ, RDI & KBI) can wake
up the MCU. All other registers and memory remain unaltered. All input/output
lines remain unchanged.
The MCU can be brought out of the STOP Mode only by a hardware interrupt or
an externally generated RESET. When exiting the STOP Mode the internal oscilla-
tor will resume after a 4064 internal processor clock cycle oscillator stabilization
delay.
6.2
WAIT INSTRUCTION
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Other Internal clocks
remain active, permitting interrupts to be generated from the Core Timer or a reset
to be generated from the COP Watchdog Timer. The Core Timer may be used to
generate a periodic exit from the WAIT Mode.
In the Wait mode, the carrier detect and the ring detect circuit can be kept
active by writing to the enable bit in the CLCSR2 register before the Wait
instruction is executed. Execution of the WAIT instruction automatically clears
the I-bit in the Condition Code Register, so that any hardware interrupt can wake
up the MCU. All other registers, memory, and input/output lines remain in their
previous states.
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