參數(shù)資料
型號: MC68HC705CL4FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 29/101頁
文件大?。?/td> 517K
代理商: MC68HC705CL4FU
February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
RESETS
MOTOROLA
REV 2.0
5-1
SECTION 5
RESETS
The MCU can be reset from four sources:
Power-On Reset (POR)
COP Watchdog Reset (COPR)
Low-Voltage Reset (LVR)
External RESET pin
All the internal peripheral modules which drive external pins will be reset by the
synchronous reset signal (RST) coming from a latch, which is synchronized to the
internal bus clock and set by the any of the four reset sources.
5.1
EXTERNAL RESET (RESET)
The RESET pin has an Schmitt trigger stage and is the only external source of a
reset. This pin is connected to a Schmitt trigger input gate to provide an upper and
lower threshold voltage separated by a minimum amount of hysteresis. This exter-
nal reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the RST signal and reset the CPU and peripherals. Termi-
nation of the external RESET input can alter the operating mode of the MCU.
NOTE
Activation of the RST signal is generally referred to as reset of the device, unless
otherwise specied.
The RESET pin can also be pulled to a low state by an internal pull-down that is
activated by the internal COP Watchdog, Power-on resets and Low Voltage Reset.
This RESET pin pull-down device will only be activated for four cycles of the inter-
nal clock, tcyc, when a COP Watchdog reset occurs; or will remain activated as
long as counting the power-on reset cycles or the low voltage is detected.
5.2
INTERNAL RESETS
The three internally generated resets are the Power-On reset , the COP Watchdog
Timer reset, and the Low-Voltage reset.
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