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參數(shù)資料
| 型號： | MC68HC705CL4FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 52/101頁 |
| 文件大小： | 517K |
| 代理商： | MC68HC705CL4FU |
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GENERAL RELEASE SPECIFICATION
February 12, 1997
MOTOROLA
TIMERS
MC68HC05CL4
8-12
REV 2.0
8.2
CORE TIMER
The Core Timer (or Ctimer) for this device is a 15-stage multi-functional ripple
counter. The features include Timer Over Flow, Power-On Reset (POR), Real
Time Interrupt, and COP Watchdog Timer
As seen in Figure 8-6, the Timer is driven by the internal bus clock divided by four
with a xed prescaler. This signal drives an 8-bit ripple counter. The value of this
8-bit ripple counter can be read by the CPU at any time by accessing the Ctimer
Counter Register (CTCR) at address $08. A timer overow function is imple-
mented on the last stage of this counter, giving a possible interrupt at the rate of
E/1024. Two additional stages produce the POR function at E/4064. The Timer
Counter Bypass circuitry (available only in Test Mode) is at this point in the timer
chain. This circuit is followed by two more stages, with the resulting clock (E/
16384) driving the Real Time Interrupt circuit. The RTI circuit consists of three
divider stages with a 1 of 4 selector. The output of the RTI circuit is further divided
by eight to drive the optional COP Watchdog Timer circuit. The RTI rate selector
bits, and the RTI and CTOF enable bits and ags are located in the Ctimer Control
and Status Register(CTCSR) at location $1A.
8.2.1 Computer Operating Properly (COP) Watchdog Reset
The COP watchdog timer function is implemented on this device by using the out-
put of the RTI circuit and further dividing it by eight. The minimum COP reset rates
are listed in Table 8-1. If the COP circuit times out, an internal reset is generated
and the normal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit 0 of address $1FF0. This
location is shared with User ROM byte. And reading this location will return the
User ROM data. When the COP is cleared, only the nal divide by eight stage
(output of the RTI) is cleared.If the COP (Computer Operating Properly) Watchdog
Timer circuit times out, an internal reset is generated and the reset vector is
fetched.
NOTE
COP Watchdog Reset function is enabled or disabled by a mask option.
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