參數(shù)資料
型號(hào): MC68HC705CL4FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 23/101頁
文件大小: 517K
代理商: MC68HC705CL4FU
GENERAL RELEASE SPECIFICATION
February 12, 1997
MOTOROLA
INTERRUPTS
MC68HC05CL4
4-4
REV 2.0
4.2
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-1. A low level input on the RESET
pin or internal generated reset signal causes the program to vector to its starting
address which is specied by the contents of memory locations $1FFE and
$1FFF. The I-bit in the condition code register is also set. The MCU is congured
to a known state during this type of reset as described in Section 5.
4.3
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts
enabled), the SWI instruction executes after interrupts which were pending before
the SWI was fetched, or before interrupts generated after the SWI was fetched.
The interrupt service routine address is specied by the contents of memory loca-
tions $1FFC and $1FFD
4.4
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. The hardware interrupts are explained in
the following sections.
4.5
EXTERNAL INTERRUPT (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts (internal
and external) are disabled. Clearing the I bit enables interrupts (subject to their
individual interrupt enable control ag status). IRQ now has an independent inter-
rupt mask bit in the Interrupt Status and Control Register (ISCR) which must also
be cleared to enable its corresponding interrupt.
The interrupt mask bit operates by inhibiting the interrupt signal after the appropri-
ate interrupt request latch. This feature allows the interrupt to be recognized and
latched even if the mask is set.
When the IRQ input goes to the active level for at least one t
ILIH, a logic one is
latched internally to signify an interrupt has been requested. When the MCU com-
pletes its current instruction, the interrupt latch is tested. If the interrupt latch con-
tains a logic one, and the interrupt mask bit (I bit) in the condition code register
and the IRQ mask bit (IRQM) in the ISCR are both clear, then the MCU can begin
the interrupt sequence. The state of the interrupt latch is reected in the interrupt
request bit (REQ) in the ISCR, and is automatically cleared during interrupt pro-
cessing. see Figure 4-2 .
IRQ interrupt requests are automatically acknowledged and cleared during inter-
rupt processing. It may also be cleared through software by setting the acknowl-
edge bit in the ISCR. Setting this bit is a “one-shot” operation and will not effect
subsequent interrupt operation. The action of clearing the acknowledge bit will
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