參數(shù)資料
型號(hào)： MC68HC705CL4FU
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 54/101頁(yè)
文件大小： 517K
代理商： MC68HC705CL4FU
GENERAL RELEASE SPECIFICATION
February 12, 1997
MOTOROLA
TIMERS
MC68HC05CL4
8-14
REV 2.0
8.2.2 Ctimer Control And Status Register (CTCSR)
The TCSR contains the timer interrupt ag, the timer interrupt enable bits, and the
real time interrupt rate select bits.
CTOF—Core Timer Overow Flag
Core Timer Over Flow bit is a clearable, read-only status bit and is set when the
8-bit ripple counter rolls over from $FF to $00. Clearing the TOF is done by writ-
ing a “0” to it. Writing a “1” to CTOF has no effect on the bit’s value. Reset
clears CTOF.
RTIF—Real Time Interrupt Flag
The Real Time Interrupt circuit consists of a three stage divider and a 1 of 4
selector. The clock frequency that drives the RTI circuit is E/213 with three addi-
tional divider stages. Real Time Interrupt Flag is a clearable, read-only status
bit and is set when the output of the chosen (1 of 4 selection) stage goes
active. Clearing the RTIF is done by writing a ’0’ to it. Writing a ’1’ to RTIF has
no effect on this bit. Reset clears RTIF.
CTOFE—Core Timer Overow Enable
When the Core Timer Over Flow Enable bit is set, a CPU interrupt request is
generated when the TOF bit is set, provided the I bit in CCR is cleared. Reset
clears this bit.
RTIE—Real Time Interrupt Enable
When the Real Time Interrupt Enable bit is set, a CPU interrupt request is gen-
erated when the RTIF bit is set, provided the I bit in the CCR is cleared. Reset
clears this bit.
RT1:RT0—Real Time Interrupt Select Bits
These two Real Time Interrupt Rate Select bits select one of four taps from the
Real Time Interrupt circuit. The settings for RTI is listed in Table 8-1. Reset sets
these RT0 and RT1, selecting the lowest periodic rate and therefore the maxi-
mum time in which to alter these bits if necessary.
CTOF
0
7
RT1
0
0000
1
6543210
0
RTIE
RT0
W
R
CTCSR
$0008
reset
CTOFE
RTIF
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