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參數(shù)資料
| 型號(hào)： | MC68HC705CL4FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 24/101頁(yè) |
| 文件大?。?/td> | 517K |
| 代理商： | MC68HC705CL4FU |
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February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
INTERRUPTS
MOTOROLA
REV 2.0
4-5
clear the request bit. This allows the programmer the option to cancel spurious
interrupts which occur while the interrupt mask bits are set. This may be neces-
sary in systems where it is desirable to prevent redundant (ghost) entries to the
interrupt service routine (where the interrupt mask is eventually cleared).
Note that the IRQM is cleared (enabled) during reset, though no interrupts can
occur until the interrupt mask bit (I-bit) of the CCR is cleared (it is set during
reset). The interrupt request latches are also cleared during reset.
Figure 4-2. Interrupt Status and Control Register
IRQM - IRQ Enable Mask
The IRQM bit is a read/write bit which will disable the IRQ interrupt when set.
IRQM is cleared by reset.
1 =
IRQ interrupt request disabled
0 =
IRQ interrupt request enabled
IRQS - IRQ Sensitivity
The IRQS bit is a read/write bit which will select whether the IRQ interrupt is
edge-sensitive only or both edge-sensitive and level-sensitive. IRQS is cleared
by reset.
1 =
both edge-sensitive and level-sensitive
0 =
edge-sensitive only
EDGE - IRQ Active Edge Select
The EDGE bit is a read/write bit which allows the user to select which edge, ris-
ing or falling, of the signal at the IRQ pin will generate an interrupt. Both rising
and falling edge sensitivity may be achieved in software by toggling the EDGE
bit from within the IRQ service routine. EDGE is cleared by reset.
1 =
Rising edge IRQ interrupt
0 =
Falling edge IRQ interrupt
REQ - IRQ Interrupt Request
The REQ bit is a read-only bit. The IRQ interrupt request bit and latch are
cleared during IRQ exception processing. Therefore, one external IRQ interrupt
pulse can be latched and subsequently serviced as soon as the I bit is cleared.
REQ will be cleared by reset.
1 =
IRQ interrupt request pending
0 =
No IRQ interrupt request pending
ISCR
$000F
7
W
R
6543210
ACK
REQ
EDGE
IRQM
0
00000000
reset
0
IRQS
0
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