參數(shù)資料
型號: MC68HC705CL4FU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數(shù): 49/101頁
文件大?。?/td> 517K
代理商: MC68HC705CL4FU
February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
TIMERS
MOTOROLA
REV 2.0
8-9
Figure 8-5. Timer State Timing Diagram For Input Capture
8.1.4 Timer Control Register (TCR)
The TCR is a read/write register containing six control bits. Three bits control inter-
rupts associated with each of the three ag bits found in the timer status register.
The other two bits control: 1) which edge is signicant to the input capture edge
detector (i.e., negative or positive), and 2) the next value to be clocked to the out-
put level register in response to a successful output compare. The timer control
register and the free running counter are the only sections of the timer affected by
reset. The TCMP pin is forced low during external reset and stays low until a valid
compare changes it to high. The timer control register is illustrated below by a def-
inition of each bit.
$FFEB
$FFED
$FFEE
$FFEF
Internal Processor Clock
T00
T01
T10
T11
Counter(16 Bit)
Input Capture Flag (ICF)
Internal Timer
Clocks
NOTE:
If the input edge occurs in the shaded area from one timer state
T10 to the other timer state T10 the input capture ag is set during the next state T11.
$FFEC
Capture
Register
Internal Capture Latch
$????
$FFED
note
Input
Edge
0
ICIE
0
7
IEDG
0
0000
X
1
6543210
0
OLVL
W
R
TCR
$0012
reset
TOIE
OCIE
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