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參數(shù)資料
| 型號： | MC68HC705CL4FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 27/101頁 |
| 文件大?。?/td> | 517K |
| 代理商： | MC68HC705CL4FU |
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February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
INTERRUPTS
MOTOROLA
REV 2.0
4-7
4.5.3 LVI Control Register
LVIE — Low Voltage Reset Enable
Low Voltage Interrupt enable bit, when set will enable an interrupt to be gener-
ated when LVIF, the low voltage interrupt ag bit is set. This bit should only be
enabled after LVRE bit in the Option Register has been set.
LVIF — Low Voltage Reset Flag
This bit is set when VDD drops below the threshold voltage of LVIth. When set
this bit will generate an interrupt provided the LVI enable bit (LVIE) is set. It can
be reset by writing a “0” to LVIF, provided VDD is above LVIth.
LVIS — Low Voltage Interrupt Status
This bit is set when VDD drops below the threshold voltage of LVIth.. The user
can read this bit to check if the LV interrupt is true or if it is just a glitch. The dif-
ference between LVIS and LVIF is that LVIF is latched while LVIS is not.
4.5.4 Ring/carrier Detect Interrupts (RDI/CDI)
This interrupt is caused by the Caller ID module when a valid Ring signal or a Car-
rier is detected. The enable and ag bits for the Ring Detect and the Carrier detect
are located in CLCSR1 register. These two interrupts will vector to separate inter-
rupt service routines located at the addresses specied by the contents of mem-
ory locations $1FF6-$1FF7 and $1FF4-$1FF5 respectively. These interrupts will
wake the MCU from the Wait mode. See Section 10.
4.5.5 Ctimer Interrupt (CORE TIMER)
The CTIMER interrupt is generated by the Core Timer when a core timer overow,
or real time interrupt has occurred as described in Section 8. The interrupt enable
bits and ags for the Core Timer interrupts are located in the Core Timer Control
and Status Register (CTCSR) located at $0008. The I-bit in the CCR must be
clear in order for the CTIMER interrupt to be enabled. These two interrupts will
vector to the same interrupt service routine located at the address specied by the
contents of memory locations $1FF2 and $1FF3.
4.5.6 Timer Interrupt (TIMER)
The TIMER interrupt is generated by the multi-function Timer when a timer over-
ow, output compare or input capture has occurred as described in Section 8.
The interrupt enable bits and ags for the Timer interrupts are located in the Timer
Control Register (TCR) and Timer Status Register (TSR) located at $0012 &
$0013. The I-bit in the CCR must be clear in order for the TIMER interrupt to be
76543210
LVSCR
$0010
READ
LVIS
LVIF
LVIE
WRITE
0
RESET
UUUUUU
0
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