
2.12 Low Power Consumption Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Wait
Time, Clock Multiplier Function)
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Chapter 2: Hardware
2.12 Low Power Consumption Control Circuits
(CPU Intermittent Operation Function, Oscillation Stabilization
Wait Time, Clock Multiplier Function)
The MB90660A has the following operating modes: PLL clock mode, PLL sleep mode, watch mode, main
clock mode, main sleep mode and stop mode. All modes other than PLL clock mode are classified as low
power consumption modes.
In main clock mode and main sleep mode, the main clock (oscillator clock) signal operates alone, the
operating clock signal is produced by dividing the main clock by two, and the PLL clock (VCO oscillator
clock) signal is stopped.
In PLL sleep mode and main sleep mode, only the CPU operating clock is stopped, and all other clock
signals operate.
In watch mode, only the timebase timer operates.
Stop mode, in which all oscillators are stopped, is the lowest power-consumption mode in which data
values are retained.
The CPU intermittent operation function allows the clock signal feed to the CPU to operate intermittently
for internal registers, internal memory, internal resources or external bus access. This enables reduced
power consumption by lowering the CPU execution speed while maintaining the high speed clock feed to
internal resources.
The PLL clock multiplier rate is set using the CS1, CS0 bits and may be either 1, 2, 3, or 4 times the clock
signal feed.
The WS1, WS0 bits can be used to set the main clock oscillation stabilization wait period after wake-up
from stop mode.
2.12.1 Register List
Reserved
MCM WS1 WS0 Reserved MCS
CS1
CS0
Bit no.
Read/write
(–)
(R)
(R/W) (R/W)
(–)
(R/W) (R/W) (R/W)
Initial value
(1)
(0)
Clock selection register
Address : 0000A1H
15
14
13
12
11
10
9
8
CKSCR
STP
SLP
SPL RST Reserved CG1
CG0 Reserved
Bit no.
Read/write
(W)
(R/W) (W)
(–)
(R/W) (R/W)
(–)
Initial value
(0)
(1)
(0)
Address : 0000A0H
7
6
5
4
3
2
1
0
LPMCR
Low power consumption Register