
1.7 Handling of Devices
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1.7 Handling of Devices
(1) Preventing Latch-Up
A phenomenon called latch-up may occur on CMOS IC devices if voltage higher than VCC or lower
than VSS is applied to input and output pins, or if voltage greater than the rated voltage is applied
between VCC and VSS. When latch-up occurs, supply current levels increase rapidly and can result in
thermal damage to semiconductor elements. Sufficient care must be taken to avoid exceeding
maximum rated values.
For the same reason, care must be taken to ensure that analog power supply levels do not exceed the
level of the digital power supply. When turning power supply on or off, be sure that analog power
supply (AVCC, AVR) and analog input levels do not exceed the digital power supply (VCC).
(2) Handling Unused Input Pins
Unused input pins can cause devices to malfunction if left open, and should therefore be pulled up or
down as appropriate.
(3) Precautions for Use of External Clock
When an external clock is used, the signal should drive the X0 pin only. Figure 1.7.1 shows an example
of an external clock connection.
Fig. 1.7.1 Example: Use of an External Clock
(4) Power Supply Pins
Whenever multiple VCC or VSS pins are used, semiconductor device design requires that all internal
elements of identical potential be connected in order to prevent latch-up. Also, they must be connected
to external power sources and grounds, in order to reduce unwanted radiation to prevent strobe signal
erratic operation due to increases in ground level, and to maintain standards for total current output.
In addition it is recommended that the VCC and VSS of this device be connected with as little impedance
as possible from the current supply source.
It is further recommended that an approx. 0.1-F ceramic capacitor be placed near the device and
connected between the VCC and VSS pins as a bypass capacitor.
X1
X0
MB90660A
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