
3.2 Resets
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3.2 Resets
3.2.1 Reset Source Generation
If a reset source is generated, this device immediately interrupts the processing currently being executed,
and begins waiting for reset release. Resets are generated by a number of different sources, as shown
below:
Generation of power-on reset
Watchdog timer overflow
Generation of external reset request through the RSTX pin
Generation of reset request through software
Both wake-up from stop mode and a power-on reset require insertion of the oscillation stabilization
period before operation can begin.
[CAUTION]
In all modes other than stop mode, the external reset input signal is sampled using the
internal clock, and therefore no reset input can be received while the external clock feed is
stopped.
Note however that the optional setting "reset input asynchronous receiving 'on'" may be
selected to forcibly set output ports (including peripheral resource outputs) in Hi-Z state.
(This optional setting is available on models MB90P663A and MB90663A/2A/1A only.)
3.2.2 Operation after Reset Release
If the reset source is withdrawn, this device immediately outputs the address where the reset vector is
stored and fetches the reset vector and mode data. The reset vector and mode data are assigned to the four
bytes FFFFDCH through FFFFDFH, and are transferred by the hardware to the registers shown in Fig. 3.2.1
after the reset is released.
Fig. 3.2.1 Reset Vector and Mode Data Storage Location and Storage Destination
Memory space
Mode data
Reset vector bits 23 to 16
Reset vector bits 15 to 8
Reset vector bits 7 to 0
F2MC-16L CPU
Mode
Register
Micro ROM
Reset sequence
FFFFDFH
FFFFDEH
FFFFDDH
FFFFDCH
PCB
PC