
2.11 Watchdog Timer, Timebase Timer Functions
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2.11.3 Detailed Register Descriptions
(1) WDTC (Watchdog timer control register)
s Register Configuration
[CAUTION]
Access by read-modify type instructions may cause abnormal operation and should not be
attempted with this register.
s Register Description
This register contains bits used to control watchdog timer functions, plus bits that identify reset sources.
s Bit Description
[Bits 7 to 3] PONR, WRST, ERST, SRST
These bits are flags that indicate reset sources. When a reset source occurs, the corresponding bit is
set as shown in Table 2.11.1. These bits are cleared to ‘0’ after a WDTC read operation. Access to
this register is read-only. Note that at power-on, the value of bits other than the power-on bit is not
warranted. Therefore software should be structured to ignore the value of other bits when the PONR
bit is ‘1.’
Table 2.11.1 Reset Source Bits and Reset Sources
[Bit 2] WTE
When the watchdog timer is in stop state, it can be returned to operating state by writing ‘0’ to this
bit. The second and subsequent writing of ‘0’ will clear the watchdog timer counter. Writing ‘1’ to
this bit has no effect.
The watchdog timer can be placed in stop state by power-on, hardware standby or watchdog timer
reset. The read value is ‘1.’
Reset source
PONR
WRST
ERST
SRST
Power-on
1
–
Watchdog timer
*
1
*
External signal pin
*
1
*
RST bit
*
1
(Asterisks (*) indicate previous value is retained.)
PONR
–
WRSTERST SRST WTE
WT1
WT0
Bit no.
Read/write
(R)
(–)
(R)
(W)
Initial value
(X)
(–)
(X)
(1)
Watchdog timer control register
Address : 0000A8H
7
6
5
4
3
2
1
0
WDTC