
2.4 Multi-Function Timer
84
Chapter 2: Hardware
(8) Zero-Detect Interrupt Control Register (ZICR)
This register controls the function to mask timer zero-detect interrupts for the specified number of
times.
Note:
Access by read-modify type instructions may cause abnormal operation and should not be
attempted with this register.
[Bit 15] IME: Interrupt mask enable bit
This bit enables a function that masks a specified number of occurrences of the timer zero-detect
interrupt source.
When ‘1’ is written to this bit, the zero-detect interrupt source is masked for the number of times
specified by the CYC3 to CYC0 bits. Thus the TZIR bit in the TCSR register is not set when an
interrupt source occurs. This also has the effect of masking interrupt requests to the CPU.
The masking function can be disabled by setting this bit to ‘0.’
This bit should not be overwritten by read-modify-write instructions.
[Bits 11 to 8] CYC3 to CYC0: Mask count setting register
These bits determine the number of times that the interrupt source will be masked.
Together, these bits configure a 4-bit reload counter, which reloads when the count value reaches
0000B. Count values can also be loaded by writing directly to this register.
The mask count equals the value set in the register, and a register setting of 0000B means that no
interrupt sources will be masked.
These bits have a buffer, so that while the timer is operating register values are written to the buffer
only and are transferred to the counter only at reload opportunities. When the timer is stopped,
values may be overwritten directly to the buffer and counter simultaneously.
IME
Description
0
Disable interrupt source mask
1
Enable interrupt source mask
IME
–
CYC3 CYC2 CYC1 CYC0
Initial value
W
ZICR
15
14
13
12
11
10
9
8
0---XXXXB
R/W
bit
–
CYC3 CYC2 CYC1 CYC0
----XXXXB
ZICBR
Address : 000047H