
2.1 CPU
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Chapter 2: Hardware
(5) Hardware Interrupt Requests during Writing to Internal Resource Areas
No hardware interrupt requests will be accepted during writing to internal resource areas. This is in
order to avoid abnormal CPU operations that can occur in response to interrupts made during rewriting
to resource interrupt control registers. Internal resource areas are not the I/O addressing area between
000000H to 0000FFH, but the areas allocated to the control registers and data registers of internal
resources.
Fig. 2.1.25 Hardware Interrupt Request during Writing to Internal Resource Areas
(6) Interrupt Suppressing Instructions
The F2MC-16L uses certain interrupt suppressing instructions that do not detect the presence of
hardware interrupt requests. See Table 2.1.11, “Hardware Interrupt Suppressing Instructions.”
(7) Multiple Interrupts
The F2MC-16L core supports multiple interrupts. Thus during processing of one interrupt, when
another interrupt of a higher level is generated, control is transferred to the higher interrupt as soon as
execution of the current instruction is ended. When processing of the stronger interrupt is completed,
control reverts to the first interrupt routine.
When another interrupt of an equal or lower level is received, the new instruction is placed on hold and
the current interrupt is processed to completion (unless indicated differently by the ILM register or I
flag setting).
Note that multiple extended intelligent I/O services cannot be initiated, so that when one extended
intelligent I/O service is being processed, all other interrupt requests and extended intelligent I/O
services will be placed on hold.
Interrupt processing
↑
Write instruction to internal resource area
…
MOV A, #08
MOV io, A
MOV A, 2000H
Interrupt request
No branch to
generated here
interrupt
Branch to interrupt
here