
2.5 UART
115
2.5.3 Detailed Register Descriptions
(1) SMR (Serial Mode Register)
Note 1:
The SMR register determines the UART operating mode. Operating mode settings should be
made while UART operations are stopped. No values should be written to this register while
the UART is operating.
Note 2:
Access to this register by read-modify-write instructions may result in abnormal operation, and
should be avoided.
[Bits 7, 6] MD1, MD0 (Mode select):
These bits select the UART operating mode
Table 2.5.1 UART Operating Mode Selection
[CAUTION]
Mode 1, asynchronous (multiprocessor) mode, allows one host CPU to operate with
multiple slave CPU units. This UART resource is unable to recognize incoming data
formats, and therefore in multi-processor mode only support operation as a master
CPU unit.
Also in this configuration the receiving parity check function cannot be used, and
therefore the PEN bit in the SCR register should be set to ‘0.’
[Bits 5 to 3] CS2, CS1, CS0 (Clock Select):
These bits select the baud rate clock source. When the dedicated baud rate generator is selected, the
baud rate can be determined at the same time.
Table 2.5.2 Clock Input Selection
[CAUTION]
When the internal timer is selected, the MB90660A series selects 16-bit timer 0.
The CS2, CS1 and CS0 bits are write-only, and have a read value of ‘1’ at all times.
[Bit 2] :Open
Mode
no.
MD1
MD0
Operating mode
0
Asynchronous (start-stop synchronized) normal mode
1
0
1
Asynchronous (start-stop synchronized) multi-processor mode
2
1
0
CLK synchronous mode
–
1
Setting prohibited
CS2 to CS0
Clock input
000B to 100B
Dedicated baud rate generator
101B
Reserved
110B
Internal timer
111B
External clock
MD1
MD0
CS2
CS1
CS0
–
SCKE SOE
Initial value
W
R/W
SMR
7
6
5
4
3
2
1
0
00000 – 00B
Address : 000024H
R/W
W