
3.5 Low Power Consumption Modes
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(5) Oscillation Stabilization Wait Period Settings
The WS1, WS0 bits are used to select the length of the oscillation stabilization wait period applied after
wake-up from stop mode. The user should select the appropriate wait period according to the
characteristics of oscillator circuits connected to the X0 and X1 pins, as well as the types of oscillation
elements used.
These bits are not initialized by any reset signals other than the power-on reset. At a power-on reset the
value is initialized to ‘11.’ As a result the oscillation stabilization wait period at power-on is
approximately 218 counts of the source oscillation.
(6) Machine Clock Switching
q Main clock/PLL clock switching
The MB90660A can switch between the main clock and PLL clock, by writing to the MCS bit in the
CKSCR register.
When the MCS bit is changed from ‘1’ to ‘0’ a PLL clock oscillation stabilization wait period
(213machine clock cycles) is applied before switching from the main clock to the PLL clock.
When the MCS bit is changed from ‘0’ to ‘1’ operation switches from the PLL clock to the main clock
at the next match between edges of the PLL clock and main clock signals (within 1 to 8 PLL clock
cycles).
Because machine clock switching does not take place immediately upon overwriting the MCS bit,
operation of resources that depend on the machine clock should be delayed until after the MCM bit is
referenced to verify the switch in machine clock speeds.
q Machine Clock Initialization
The MCS bit is not initialized by resets from external pins or the RST bit. The initial value following a
reset is ‘1.’