
2.4 Multi-Function Timer
93
(5) Count Mode
When the MODE bit in the TMCR register is set to '0,' the timer operates in up-count mode. In
up-count mode, each time the timer value matches the compare-clear register, the timer is cleared
to 0000H and continues counting upward.
When the MODE bit is set to '1' the timer operates in up/down count mode. In up/down count
mode, each time the timer value matches the compare-clear register, the timer switches direction
from up-count to down-count. When the timer value reaches 0000H, the count switches direction
again, from down-count to up-count.
Fig. 2.4.5 Operation in Two Count Modes
(6) Compare-Clear Operation
Whenever a match is detected between the compare-clear register and the timer value, the timer
control block sends out a match signal to set the TMIR bit in the TCSR register, which controls
the timer count.
If the timer is operating in up-count mode, the occurrence of a compare-clear match clears the
timer to 0000H at the next count, and the count continues.
If the timer is operating in up/down count mode, the occurrence of a compare-clear match
switches the direction at the next count, and the timer continues to count downwards.
Fig. 2.4.6 Compare-Clear Operation
Operation in Up-Count Mode
Timer value
Timer start
Compare-clear
Time
Operation in Up/Down Count Mode
Zero detected
CLRR
Timer value
Time
CLRR
match detected
Timer start
Compare-clear
match detected
Compare-clear
match detected
Count clock
Timer value
Compare-clear match
00
Up count mode
Up/down count mode
α : compare-clear register value
01
02
α
α-1
Count clock
Timer value
Compare-clear match
α-1
α-2
α
α-1