
2.5 UART
116
Chapter 2: Hardware
[Bit 1] SCKE (SCLK enable):
For communication in CLK synchronous mode (mode 2), this bit determines whether the SCK pin is
used as a clock input pin or a clock output pin.
In CLK asynchronous modes or external clock mode, this bit should be set to ‘0.’
0: SCK pin functions as clock input pin
1: SCK pin functions as clock output pin
[CAUTION]
When an external clcok source is selected, this pin must function as the clock input
pin.
[Bit 0] SOE (Serial output enable):
This bit determines whether external pins (SOT) that also can be used as general-purpose I/O ports
will function as serial output pins or as I/O port pins.
0: General-purpose I/O port pin function
1: Serial data output pin (SOT) function
(2) SCR (Serial Control Register)
The SCR register controls the transfer protocol used for serial transmission.
[Bit 15] PEN (Parity enable):
This bit determines whether parity bits are attached to data in serial transmission.
0: No parity
1: Parity
[CAUTION]
Parity bit attachment is available only in asynchronous (start-stop synchronized)
communications in normal mode (mode 0). In multi-processor mode (mode 1) and
CLK-synchronous communication (mode 2), no parity bits may be attached.
[Bit 14] P (Parity):
This bit selects even or odd parity for data communications in which a parity bit is used.
0: Even parity
1: Odd parity
[Bit 13] SBL (Stop bit length):
This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop
synchronized) communication.
0: 1 stop bit
1: 2 stop bits
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Initial value
R/W
W
R/W
SCR
15
14
13
12
11
10
9
8
00000100B
Address : 000025H
R/W