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3.8 Standby Mode (Low Power Consumption)
3.8.4
Watch Mode
This section describes the operations in watch mode.
I
Operations in watch mode
H
Transition to the watch mode
The watch mode is a mode which stops the operating clock of CPU and main peripheral circuits.
A transition to the watch mode is only possible from the subclock mode (The main clock
oscillation is stopped).
Contents of the registers and RAM just before transition to the watch mode are retained and
most functions other than the watch prescaler (watch interrupt), external interrupt circuits, and
part of the functions operating on the subclock are stopped. Thus, data can be retained with
very low power consumption.
A transition to the watch mode is caused by writing "1" into the clock bit (STBC: TMD) of the
standby control register when the subclock mode is set by the system clock select bit of the
system clock control register.
If the pin state designate bit (STBC: SPL) of the standby control register during transition to the
watch mode is "0", the external pin states are retained. If the bit is "1", external pins are put into
high impedance.
If an interrupt request has occurred when "1" is written into the TMD bit, the write operation is
ignored and execution of instructions continues without making a transition to the watch mode
(No transition to the watch mode occurs even after interrupt processing is completed).
H
Watch mode release
The watch mode can be released by a reset, watch interrupt, or external interrupt.
If a reset occurs in watch mode, the reset operation is performed after taking the oscillation
stabilization wait time of the main clock.
Pin states are initialized by the reset.
If an interrupt request whose interrupt level is higher than "11" comes from the watch prescaler
or an external interrupt circuit in watch mode, the watch mode is released regardless of the
interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1, 0) of CPU. Since most
peripheral functions other than the watch prescaler are stopped in watch mode, no interrupt
requests other than watch interrupts and external interrupts occur.
After releasing the watch mode, a normal interrupt operation is performed. If the interrupt is
accepted, interrupt processing is performed. If the interrupt is not accepted, execution starts
with the instruction following the instruction executed just before transition to the watch mode.
If the watch mode is released, part of the peripheral functions restarts halfway through their
operations. Thus, for example, the first interval time of the interval timer function is undefined.
Each peripheral function should be initialized after returning from the watch mode.