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9.5 16-bit Timer/Counter Interrupts
9.5
16-bit Timer/Counter Interrupts
A 16-bit timer/counter interrupt is caused by:
An overflow in interval timer function mode (FFFF
H
--> 0000
H
)
An overflow in the 16-bit counter function mode (FFFF
H
--> 0000
H
)
I
Interrupts in Interval Timer Function Mode
If the counter counts up from the defined counter value according to the internal count clock
until it overflows, the interrupt request flag bit (TMCR: TCEF) is set to 1. If, at this time, the
interrupt request enable bit is set to Enabled (TMCR: TCIE=1), an interrupt request (IRQD)
occurs in the CPU.
Use the interrupt processing routine to write 0 to the TCEF bit and clear the interrupt request.
If the counter is cleared (TMCR: TCR=0) and the counter value overflows at the same time, the
TCEF bit is not set. While the TCEF bit is 1, setting the TCIE bit from Disabled to Enabled (0 to
1) immediately causes an interrupt request.
The TCEF bit is set whenever the counter value overflows regardless of the value in the TCIE
bit.
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Interrupts in Counter Function Mode
If the counter counts up from the defined counter value each time preset edge is detected until it
overflows, the interrupt request flag bit (TMCR: TCEF) is set to 1. If, at this time, the interrupt
request enable bit is set to Enabled (TMCR: TCIE=1), an interrupt request (IRQD) occurs in the
CPU.
Use the interrupt processing routine to write 0 to the TCEF bit and clear the interrupt request.
If the counter is cleared (TMCR: TCR=0) and the counter value overflows at the same time, the
TCEF bit is not set. While the TCEF bit is 1, setting the TCIE bit from Disabled to Enabled (0 to
1) immediately causes an interrupt request.
The TCEF bit is set whenever the counter value overflows regardless of the value in the TCIE
bit.
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Register Related to the Interrupts of the 16-bit Timer/Counter and the Vector Table
For the operation of interrupts, see Section 3.4.2 "Interrupt Processing".
Table 9.5-1 Register Related to the Interrupts of the 16-bit Timer/Counter and the Vector
Table
Interrupt
name
Interrupt level setting register
Vector table address
Register
Bit to be set
Upper
Lower
IRQD
ILR4 (007E
H
)
LD1 (bit 3)
LD0 (bit 2)
FFE0
H
FFE1
H