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CHAPTER 8 8/16-BIT TIMER/COUNTER
8.10 Status of the 8/16-bit Timer/Counter in Each Mode
This section describes the operations of switching to the sleep and stop modes and
receiving a suspend request during the operation of the 8/16-bit timer/counter.
I
Operation in the Subclock and Standby Modes and when the Counter is Suspended
Figure 8.10-1 "Operation in the Subclock and Standby Modes and when the Counter is
Suspended" shows the counter value statuses upon switching to the sleep and stop modes and
receiving a suspend request while the interval timer or counter function is operating.
In the stop mode, the counter stops, maintaining the value. If the stop mode is cleared by an
external interrupt, the counter starts counting from the maintained value. Therefore, the initial
interval time and the external clock count cannot be correct values. After the stop mode is
cleared, initialize the 8/16-bit timer/counter again.
The operations of switching to and clearing the watch mode (STBC: TMD=1) is the same as the
operation of switching to and clearing the stop mode. The watch mode is cleared by a watch
interrupt and an external interrupt.
If the counter is suspended (T1STP=1), the counter stops, maintaining the value. If the
operation is continued (T1STP=0), the count operation is restarted.
Figure 8.10-1 Operation in the Subclock and Standby Modes and when the Counter is Suspended
Time
Counter value
0000
H
Match
Match
Match
Counter clear
Match
Match
STR1 bit
T1IF bit
(T1IE bit)
T01 terminal
SLP bit
(STBC register)
STP bit
(STBC register)
*
Sleep
Sleep cleared by IRQ5
Stop
External
interrupt
STP1 bit
Suspend
Cleared by the program
Data register
setting value
Start
*1: If the terminal status specification bit in the standby control register (STBC: SPL) is set to "1" and
the T01 terminal is not pulled up (optional), the T01 terminal in the stop mode has a high impedance.
If the SPL bit is "0", the value immediately before entering the stop mode is maintained.