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7.6 Notes on Using the Watch Prescaler
7.6
Notes on Using the Watch Prescaler
The following describes the precautions when using the watch prescaler.
The watch prescaler cannot be used when a single clock source is specified with the
option setting.
I
Notes on Using the Watch Prescaler
H
Precautions when setting the watch prescaler in programs
It is impossible to return from interrupt processing if the interrupt request flag bit (WPCR: WIF) is
"1" and the interrupt request enable bit is set (WPCR: WIF=1). The WIF bit must be cleared.
H
Clearing the watch prescaler
The watch prescaler is cleared, in addition to clearing by the watch prescaler clear bit (WPCR:
WCLR=0), when the oscillation stabilization wait time of the subclock is required.
If the watch prescaler is selected (WDTC: CS=1) as the count clock of the watchdog timer, the
watchdog timer is also cleared when the watch prescaler is cleared.
H
Using the watch prescaler as a timer for the oscillation stabilization wait time
Since the subclock oscillation is stopped when the power is turned on or operating in sub-stop
mode, the oscillator takes the oscillation stabilization wait time using the watch prescaler after
activating operations.
Do not make a transition from the main clock mode to the subclock mode during oscillation
stabilization wait time, such as just after power-on.
The oscillation stabilization wait time of the subclock is fixed.
For details, see Section 3.7.5 "Oscillation Stabilization Wait Time".
H
Precautions when using watch interrupts
In main stop mode, the watch prescaler performs a count operation but a watch interrupt (IRQ8)
does not occur.
H
Precautions when using the peripheral functions that use clocks supplied from the
prescaler.
If the counter of the watch prescaler is cleared, the "H" level of the clock supplied by the watch
prescaler is short and its "L" level may be longer by a maximum of 1/2 cycle because the output
originates from the initial state.
Though the clock for the watchdog timer is also output from the initial state, the watchdog timer
works in normal cycles because the counter of the watchdog timer is cleared simultaneously.